A detailed ASIC implementation study of a decoder architecture for the prod-uct of two Reed-Solomon (RS) codes is presented. The implementation aims to achieve high throughput (more than 1 Tb/s) under low power and area consump-tion constraints while having more than 9 dB coding gain compared to uncoded transmission when concatenated with an inner polar code. The scope of work includes a comprehensive design space exploration for very high rate RS codes. Novel algorithms and architectures are introduced to achieve the design goals. High-throughput is achieved through a combination of pipelining and unrolling methods, while a fully-automated register balancing technique is used to mini-mize the implementation complexity. The implementation has been carried out using the 28nm TSMC library.