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      Reliability-aware 3D chip multiprocessor design

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      Author(s)
      Öztürk, Özcan
      Aktürk, İsmail
      Date
      2012-06
      Source Title
      Manufacturable and dependable multicore architectures at nanoscale (MEDIAN'12)
      Publisher
      IEEE
      Language
      English
      Type
      Conference Paper
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      Abstract
      Ability to stack separate chips in a single package enables three-dimensional integrated circuits (3D ICs). Heterogeneous 3D ICs provide even better opportunities to reduce the power and increase the performance per unit area. An important issue in designing a heterogeneous 3D IC is reliability. To achieve this, one needs to select the data mapping and processor layout carefully. In this paper, we try to perform this mapping and processor layout effectively. Specifically, on a heterogeneous 3D CMP, we explore how applications can be mapped onto 3D ICs to maximize reliability. Our preliminary experimental evaluation indicates that the proposed technique generates promising results in both reliability and performance.
      Keywords
      Reliability
      Multicore
      3D
      Data mapping
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      http://hdl.handle.net/11693/52289
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      • Department of Computer Engineering 1561
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