Reliability-aware 3D chip multiprocessor design

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dc.contributor.authorÖztürk, Özcanen_US
dc.contributor.authorAktürk, İsmailen_US
dc.coverage.spatialAnnecy, Franceen_US
dc.date.accessioned2019-08-02T07:44:38Z
dc.date.available2019-08-02T07:44:38Z
dc.date.issued2012-06en_US
dc.descriptionDate of Conference: June 2012
dc.descriptionConference name: Proceedings of the Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12)
dc.description.abstractAbility to stack separate chips in a single package enables three-dimensional integrated circuits (3D ICs). Heterogeneous 3D ICs provide even better opportunities to reduce the power and increase the performance per unit area. An important issue in designing a heterogeneous 3D IC is reliability. To achieve this, one needs to select the data mapping and processor layout carefully. In this paper, we try to perform this mapping and processor layout effectively. Specifically, on a heterogeneous 3D CMP, we explore how applications can be mapped onto 3D ICs to maximize reliability. Our preliminary experimental evaluation indicates that the proposed technique generates promising results in both reliability and performance.en_US
dc.identifier.urihttp://hdl.handle.net/11693/52289
dc.language.isoEnglishen_US
dc.publisherIEEE
dc.source.titleManufacturable and dependable multicore architectures at nanoscale (MEDIAN'12)en_US
dc.subjectReliabilityen_US
dc.subjectMulticoreen_US
dc.subject3Den_US
dc.subjectData mappingen_US
dc.titleReliability-aware 3D chip multiprocessor designen_US
dc.typeConference Paperen_US
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