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      Slicing based code parallelization for minimizing inter-processor communication

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      Author
      Kandemir, M.
      Zhang, Y.
      Muralidhara, S. P.
      Öztürk, Özcan
      Narayanan, S. H. K.
      Date
      2009-10
      Source Title
      CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
      Publisher
      ACM
      Pages
      87 - 95
      Language
      English
      Type
      Conference Paper
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      Abstract
      One of the critical problems in distributed memory multi-core architectures is scalable parallelization that minimizes inter-processor communication. Using the concept of iteration space slicing, this paper presents a new code parallelization scheme for data-intensive applications. This scheme targets distributed memory multi-core architectures, and formulates the problem of data-computation distribution (partitioning) across parallel processors using slicing such that, starting with the partitioning of the output arrays, it iteratively determines the partitions of other arrays as well as iteration spaces of the loop nests in the application code. The goal is to minimize inter-processor data communications. Based on this iteration space slicing based formulation of the problem, we also propose a solution scheme. The proposed data-computation scheme is evaluated using six data-intensive benchmark programs. In our experimental evaluation, we also compare this scheme against three alternate data-computation distribution schemes. The results obtained are very encouraging, indicating around 10% better speedup, with 16 processors, over the next-best scheme when averaged over all benchmark codes we tested. Copyright 2009 ACM.
      Keywords
      Automatic code parallelization
      Code analysis and optimization
      Iteration space slicing
      Parallelizing compilers
      Automatic codes
      Code analysis
      Iteration space slicing
      Iteration spaces
      Parallelizations
      Parallelizing compiler
      Embedded systems
      Optimization
      Parallel architectures
      Program compilers
      Permalink
      http://hdl.handle.net/11693/28611
      Published Version (Please cite this version)
      http://dx.doi.org/10.1145/1629395.1629409
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      • Department of Computer Engineering 1368
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