Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect
IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
IEEE Computer Society
296 - 301
MetadataShow full item record
Please cite this item using this persistent URLhttp://hdl.handle.net/11693/28038
Due to architectural complexity and process costs, circuit-level solutions are often the preferred means to resolving signal integrity issues that affect the performance and reliability of on-chip interconnect. In this paper, we consider multi-segment bit-lines used in wide on-chip interconnect, and explore in detail the effect of signal transition skew on the delay and time of flight in the presence of crosstalk. We present the relationship between segment delay, signal transition skew and the injected noise pulse and propose a novel staggered latch bus architecture to explicitly exploit transition skew for improved speed and performance. Our proposed SLB architecture achieves an average of 2.5X (2.3X) improvement in speed for fully-aligned (mis-aligned) buffering schemes with no increase in area, power or additional wires needed. © 2013 IEEE.