Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect

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dc.citation.epage301en_US
dc.citation.spage296en_US
dc.contributor.authorEze, M.en_US
dc.contributor.authorÖztürk, Özcanen_US
dc.contributor.authorNarayanan V.en_US
dc.coverage.spatialIstanbul, Turkeyen_US
dc.date.accessioned2016-02-08T12:09:18Z
dc.date.available2016-02-08T12:09:18Z
dc.date.issued2013en_US
dc.departmentDepartment of Computer Engineeringen_US
dc.descriptionDate of Conference: 7-9 Oct. 2013en_US
dc.description.abstractDue to architectural complexity and process costs, circuit-level solutions are often the preferred means to resolving signal integrity issues that affect the performance and reliability of on-chip interconnect. In this paper, we consider multi-segment bit-lines used in wide on-chip interconnect, and explore in detail the effect of signal transition skew on the delay and time of flight in the presence of crosstalk. We present the relationship between segment delay, signal transition skew and the injected noise pulse and propose a novel staggered latch bus architecture to explicitly exploit transition skew for improved speed and performance. Our proposed SLB architecture achieves an average of 2.5X (2.3X) improvement in speed for fully-aligned (mis-aligned) buffering schemes with no increase in area, power or additional wires needed. © 2013 IEEE.en_US
dc.identifier.doi10.1109/VLSI-SoC.2013.6673296en_US
dc.identifier.urihttp://hdl.handle.net/11693/28038
dc.language.isoEnglishen_US
dc.publisherIEEEen_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/VLSI-SoC.2013.6673296en_US
dc.source.title2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)en_US
dc.subjectBus architectureen_US
dc.subjectMulti-segmenten_US
dc.subjectOn chip interconnecten_US
dc.subjectPerformance and reliabilitiesen_US
dc.subjectSignal Integrityen_US
dc.subjectSignal transitionen_US
dc.subjectSwitched architectureen_US
dc.subjectTime of flighten_US
dc.subjectInterconnection networksen_US
dc.titleStaggered latch bus: A reliable offset switched architecture for long on-chip interconnecten_US
dc.typeConference Paperen_US
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