Terabits-per-second throughput for polar codes

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buir.contributor.authorSüral, Altuğ
buir.contributor.authorSezer, E. Göksu
buir.contributor.authorErtuğrul, Yiğit
buir.contributor.authorArıkan, Orhan
buir.contributor.authorArıkan, Erdal
buir.contributor.orcidArıkan, Orhan|0000-0002-3698-8888
dc.citation.epage7en_US
dc.citation.spage1en_US
dc.contributor.authorSüral, Altuğen_US
dc.contributor.authorSezer, E. Göksuen_US
dc.contributor.authorErtuğrul, Yiğiten_US
dc.contributor.authorArıkan, Orhanen_US
dc.contributor.authorArıkan, Erdalen_US
dc.coverage.spatialİstanbul, Turkeyen_US
dc.date.accessioned2020-01-30T07:49:56Z
dc.date.available2020-01-30T07:49:56Z
dc.date.issued2019-09
dc.departmentDepartment of Electrical and Electronics Engineeringen_US
dc.descriptionDate of Conference: 8-8 Sept. 2019en_US
dc.descriptionConference name: 2019 IEEE 30th International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC Workshops)en_US
dc.description.abstractBy using Majority Logic (MJL) aided Successive Cancellation (SC) decoding algorithm, an architecture and a specific implementation for high throughput polar coding are proposed. SC-MJL algorithm exploits the low complexity nature of SC decoding and the low latency property of MJL. In order to reduce the complexity of SC-MJL decoding, an adaptive quantization scheme is developed within 1-5 bits range of internal log-likelihood ratios (LLRs). The bit allocation is based on maximizing the mutual information between the input and output LLRs of the quantizer. This scheme causes a negligible performance loss when the code block length is N= 1024 and the number of information bits is K = 854. The decoder is implemented on 45nm ASIC technology using deeply-pipelined, unrolled hardware architecture with register balancing. The pipeline depth is kept at 40 clock cycles in ASIC by merging consecutive decoding stages implemented as combinational logic. The ASIC synthesis results show that SC-MJL decoder has 427 Gb/s throughput at 45nm technology. When we scale the implementation results to 7nm technology node, the throughput reaches 1 Tb/s with under 10 mm 2 chip area and 0.37 W power dissipation.en_US
dc.identifier.doi10.1109/PIMRCW.2019.8880815en_US
dc.identifier.eissn1558-2612
dc.identifier.urihttp://hdl.handle.net/11693/52919
dc.language.isoEnglishen_US
dc.publisherIEEEen_US
dc.relation.isversionofhttps://doi.org/10.1109/PIMRCW.2019.8880815en_US
dc.source.title2019 IEEE 30th International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC Workshops)en_US
dc.subjectApplication specific integrated circuitsen_US
dc.subjectPolar codesen_US
dc.subjectTerabits-per-second throughputen_US
dc.subjectSuccessivecancellation decodingen_US
dc.subjectMajority-logic decodingen_US
dc.subjectQuantizationen_US
dc.titleTerabits-per-second throughput for polar codesen_US
dc.typeConference Paperen_US

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