A cache topology-aware multi-query scheduler for multicore architectures

dc.citation.epage87en_US
dc.citation.spage86en_US
dc.contributor.authorOrhan, U.en_US
dc.contributor.authorDing, W.en_US
dc.contributor.authorYedlapalli, P.en_US
dc.contributor.authorKandemir, M.en_US
dc.contributor.authorÖztürk, Özcanen_US
dc.coverage.spatialRaleigh, NC, USAen_US
dc.date.accessioned2016-02-08T12:27:10Zen_US
dc.date.available2016-02-08T12:27:10Zen_US
dc.date.issued2014en_US
dc.departmentDepartment of Computer Engineeringen_US
dc.descriptionConference name: 2014 IEEE International Symposium on Workload Characterization (IISWC)en_US
dc.descriptionDate of Conference: 26-28 October 2014en_US
dc.description.abstractGrowing performance gap between processors and main memory has made it worthwhile to consider off-chip data accesses in multi-query processing [2], [1], [3]. Exploiting data-sharing opportunities among concurrent queries can be critical for effective utilization of the underlying shared memory hierarchy. Given a set of queries, there may be a common retrieval operation for several cases to the same data. A query can benefit from the data previously loaded into the shared cache/memory space by another query. However, if these queries are scheduled independently, it is very likely that the same data is brought from off-chip memory to on-chip caches multiple times, thereby consuming off-chip bandwidth and slowing down overall execution.en_US
dc.identifier.doi10.1109/IISWC.2014.6983047en_US
dc.identifier.isbn978-1-4799-6452-9en_US
dc.identifier.urihttp://hdl.handle.net/11693/28685en_US
dc.language.isoEnglishen_US
dc.publisherIEEEen_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/IISWC.2014.6983047en_US
dc.source.titleIEEE International Symposium on Workload Characterization (IISWC)en_US
dc.titleA cache topology-aware multi-query scheduler for multicore architecturesen_US
dc.typeConference Paperen_US
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