Spatiotemporal graph and hypergraph partitioning models for sparse matrix-vector multiplication on many-core architectures

buir.contributor.authorAbubaker, Nabil
buir.contributor.authorAykanat, Cevdet
dc.citation.epage458en_US
dc.citation.issueNumber2en_US
dc.citation.spage445en_US
dc.citation.volumeNumber30en_US
dc.contributor.authorAbubaker, Nabilen_US
dc.contributor.authorAkbudak, K.en_US
dc.contributor.authorAykanat, Cevdeten_US
dc.date.accessioned2020-02-05T08:47:00Z
dc.date.available2020-02-05T08:47:00Z
dc.date.issued2019
dc.departmentDepartment of Computer Engineeringen_US
dc.description.abstractThere exist graph/hypergraph partitioning-based row/column reordering methods for encoding either spatial or temporal locality for sparse matrix-vector multiplication (SpMV) operations. Spatial and temporal hypergraph models in these methods are extended to encapsulate both spatial and temporal localities based on cut/uncut net categorization obtained from vertex partitioning. These extensions of spatial and temporal hypergraph models encode the spatial locality primarily and the temporal locality secondarily, and vice-versa, respectively. However, the literature lacks models that simultaneously encode both spatial and temporal localities utilizing only vertex partitioning for further improving the performance of SpMV on shared-memory architectures. In order to fill this gap, we propose a novel spatiotemporal hypergraph model that leads to a one-phase spatiotemporal reordering method which encodes both types of locality simultaneously. We also propose a framework for spatiotemporal methods which encodes both types of locality in two dependent phases and two separate phases. The validity of the proposed spatiotemporal models and methods are tested on a wide range of sparse matrices and the experiments are performed on both a 60-core Intel Xeon Phi processor and a Xeon processor. Results show the validity of the methods via almost doubling the Gflop/s performance through enhancing data locality in parallel SpMV operations.en_US
dc.description.provenanceSubmitted by Zeynep Aykut (zeynepay@bilkent.edu.tr) on 2020-02-05T08:47:00Z No. of bitstreams: 1 Spatiotemporal_graph_and_hypergraph_partitioning_models_for_sparse_matrix_vector_multiplication_on_many_core_architectures.pdf: 1328105 bytes, checksum: 5ef4ed751a763ab299d0c21b5bcb240b (MD5)en
dc.description.provenanceMade available in DSpace on 2020-02-05T08:47:00Z (GMT). No. of bitstreams: 1 Spatiotemporal_graph_and_hypergraph_partitioning_models_for_sparse_matrix_vector_multiplication_on_many_core_architectures.pdf: 1328105 bytes, checksum: 5ef4ed751a763ab299d0c21b5bcb240b (MD5) Previous issue date: 2019en
dc.identifier.doi10.1109/TPDS.2018.2864729en_US
dc.identifier.issn1045-9219en_US
dc.identifier.urihttp://hdl.handle.net/11693/53082en_US
dc.language.isoEnglishen_US
dc.publisherIEEE Computer Societyen_US
dc.relation.isversionofhttps://dx.doi.org/10.1109/TPDS.2018.2864729en_US
dc.source.titleIEEE Transactions on Parallel and Distributed Systemsen_US
dc.subjectSparse matrixen_US
dc.subjectSparse matrix-vector multiplicationen_US
dc.subjectData localityen_US
dc.subjectSpatial localityen_US
dc.subjectTemporal localityen_US
dc.subjectHypergraph modelen_US
dc.subjectBipartite graph modelen_US
dc.subjectGraph modelen_US
dc.subjectHypergraph partitioningen_US
dc.subjectGraph partitioningen_US
dc.subjectIntel many integrated core architectureen_US
dc.subjectIntel Xeon Phien_US
dc.titleSpatiotemporal graph and hypergraph partitioning models for sparse matrix-vector multiplication on many-core architecturesen_US
dc.typeArticleen_US

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