Design of a high efficiency power amplifier by using Doherty configuration

Abstract

Power amplifiers (PAs) have their highest efficiency when they are used at full power (0dB back-off). For this reason, most PAs are used at 1dB compression point (P1dB), but this point is highly nonlinear. For high linearity, PAs should be used at some back-off value (below the point of 1dB compression point). In this case the efficiency of PAs decreases drastically. Another issue is that widely used digital modulation techniques produce signals which has a large peak-to-average power ratio (PAPR). In modern systems the power is reduced automatically to use spectrum efficiently and to prevent interference and detection. These conditions force new PA designs to have both high linearity and high efficiency from P1dB point down to a few dB back-off region.Doherty Amplifier technique uses Class-AB and Class-C amplifiers in parallel, and an increase in the efficieny especially at back-off regions occurs. By the use of parallel configuration P1dB point is improved. In the thesis, the theory of Doherty Configuration is explained, a Doherty Amplifier working at 4.75GHz is designed and simulated. A balanced amplifier is also designed and the results of both amplifiers are compared. The P1dB points of balanced amplifier and Doherty Amplifier are nearly same. In the Doherty case, a significant increase in efficiency is obtained at 6-dB back-off point and a little increase in efficiency is obtained at P1dB point. A Doherty Amplifier at 2GHz is implemented and its efficiency and linearity is compared with the implemented single amplifier. Significant increases are achieved both at P1dB point and at the efficiency.