NS-SRAM: neighborhood solidarity SRAM for reliability enhancement of SRAM memories

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dc.citation.epage159en_US
dc.citation.spage154en_US
dc.contributor.authorAlouani, I.en_US
dc.contributor.authorAhangari, Hamzehen_US
dc.contributor.authorÖztürk, Özcanen_US
dc.contributor.authorNiar, S.en_US
dc.coverage.spatialLimassol, Cyprus
dc.date.accessioned2018-04-12T11:50:09Z
dc.date.available2018-04-12T11:50:09Z
dc.date.issued2016-08-09en_US
dc.departmentDepartment of Computer Engineeringen_US
dc.descriptionDate of Conference: 31 Aug.-2 Sept. 2016
dc.descriptionConference name: 2016 Euromicro Conference on Digital System Design (DSD)
dc.description.abstractTechnology shift and voltage scaling increased the susceptibility of Static Random Access Memories (SRAMs) to errors dramatically. In this paper, we present NS-SRAM, for Neighborhood Solidarity SRAM, a new technique to enhance error resilience of SRAMs by exploiting the adjacent memory bit data. Bit cells of a memory line are paired together in circuit level to mutually increase the static noise margin and critical charge of a cell. Unlike existing techniques, NS-SRAM aims to enhance both Bit Error Rate (BER) and Soft Error rate (SER) at the same time. Due to auto-adaptive joiners, each of the adjacent cells' nodes is connected to its counterpart in the neighbor bit. NS-SRAM enhances read-stability by increasing critical Read Static Noise Margin (RSNM), thereby decreasing faults when circuit operates under voltage scaling. It also increases hold-stability and critical charge to mitigate soft-errors. By the proposed technique, reliability of SRAM based structures such as cache memories and register files can drastically be improved with comparable area overhead to existing hardening techniques. Moreover it does not require any extra-memory, does not impact the memory effective size, and has no negative impact on performance. © 2016 IEEE.en_US
dc.description.provenanceMade available in DSpace on 2018-04-12T11:50:09Z (GMT). No. of bitstreams: 1 bilkent-research-paper.pdf: 179475 bytes, checksum: ea0bedeb05ac9ccfb983c327e155f0c2 (MD5) Previous issue date: 2016en
dc.identifier.doi10.1109/DSD.2016.12en_US
dc.identifier.urihttp://hdl.handle.net/11693/37753
dc.language.isoEnglishen_US
dc.publisherIEEEen_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/DSD.2016.12en_US
dc.source.title2016 Euromicro Conference on Digital System Design (DSD)en_US
dc.subjectReliabilityen_US
dc.subjectSNMen_US
dc.subjectSoft errorsen_US
dc.subjectSRAMen_US
dc.subjectBit error rateen_US
dc.subjectCache memoryen_US
dc.subjectComputer controlen_US
dc.subjectDigital storageen_US
dc.subjectError correctionen_US
dc.subjectErrorsen_US
dc.subjectRadiation hardeningen_US
dc.subjectRandom access storageen_US
dc.subjectRandom errorsen_US
dc.subjectReliabilityen_US
dc.subjectSystems analysisen_US
dc.subjectVoltage scalingen_US
dc.subjectError resilienceen_US
dc.subjectRead static noise margin (RSNM)en_US
dc.subjectReliability enhancementen_US
dc.subjectSoft erroren_US
dc.subjectSoft error rateen_US
dc.subjectStatic noise marginen_US
dc.subjectStatic random access memoryen_US
dc.subjectTechnology shiften_US
dc.subjectStatic random access storageen_US
dc.titleNS-SRAM: neighborhood solidarity SRAM for reliability enhancement of SRAM memoriesen_US
dc.typeConference Paperen_US

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