Hardware/software approaches for reducing the process variation impact on instruction fetches

Date
2013
Authors
Kadayif, I.
Turkcan, M.
Kiziltepe, S.
Ozturk, O.
Advisor
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Source Title
ACM Transactions on Design Automation of Electronic Systems
Print ISSN
1084-4309
Electronic ISSN
Publisher
ACM New York, NY
Volume
18
Issue
4
Pages
54:1 - 54:23
Language
English
Type
Article
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Abstract

As technology moves towards finer process geometries, it is becoming extremely difficult to control critical physical parameters such as channel length, gate oxide thickness, and dopant ion concentration. Variations in these parameters lead to dramatic variations in access latencies in Static Random Access Memory (SRAM) devices. This means that different lines of the same cache may have different access latencies. A simple solution to this problem is to adopt the worst-case latency paradigm. While this egalitarian cache management is simple, it may introduce significant performance overhead during instruction fetches when both address translation (instruction Translation Lookaside Buffer (TLB) access) and instruction cache access take place, making this solution infeasible for future high-performance processors. In this study, we first propose some hardware and software enhancements and then, based on those, investigate several techniques to mitigate the effect of process variation on the instruction fetch pipeline stage in modern processors. For address translation, we study an approach that performs the virtual-to-physical page translation once, then stores it in a special register, reusing it as long as the execution remains on the same instruction page. To handle varying access latencies across different instruction cache lines, we annotate the cache access latency of instructions within themselves to give the circuitry a hint about how long to wait for the next instruction to become available. © 2013 ACM.

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Keywords
Address translation, Encoding, Process variation, Instruction cache, Address translation
Citation
Published Version (Please cite this version)