An efficient parallelization technique for high throughput FFT-ASIPs

Date
2006
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Source Title
2006 IEEE International Symposium on Circuits and Systems
Print ISSN
0271-4310
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Publisher
IEEE
Volume
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Pages
5664 - 5667
Language
English
Type
Conference Paper
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Abstract

Fast Fourier Transformation (FFT) and it's inverse (IFFT) are used in Orthogonal Frequency Division Multiplexing (OFDM) systems for data (de)modulation. The transformations are the kernel tasks in an OFDM implementation, and are the most processing-intensive ones. Recent trends in the electronic consumer market require OFDM implementations to be flexible, making a trade-off between area, energy-efficiency, flexibility and timing a necessity. This has spurred the development of Application-Specific Instruction-Set Processors (ASIPs) for FFT processing. Parallelization is an architectural parameter that significantly influence design goals. This paper presents an analysis of the efficiency of parallelization techniques for an FFT-ASIP. It is shown that existing techniques are inefficient for high throughput applications such as Ultra Wideband (UWB), because of memory bottlenecks. Therefore, an interleaved execution technique which exploits temporal parallelism is proposed. With this technique, it is possible to meet the throughput requirement of UWB (409.6 Msamples/s) with only 4 non-trivial butterfly units for an ASIP that runs at 400MHz. © 2006 IEEE.

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Keywords
Energy efficiency, Fast Fourier transforms, Orthogonal frequency division multiplexing, Parameter estimation, Program processors, Application-Specific Instruction-Set Processors (ASIP), Architectural parameter, Parallel processing systems
Citation
Published Version (Please cite this version)