An FPGA implementation architecture for decoding of polar codes

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dc.citation.epage441en_US
dc.citation.spage437en_US
dc.contributor.authorPamuk, Alptekinen_US
dc.coverage.spatialAachen, Germanyen_US
dc.date.accessioned2016-02-08T12:16:58Z
dc.date.available2016-02-08T12:16:58Z
dc.date.issued2011en_US
dc.departmentDepartment of Electrical and Electronics Engineeringen_US
dc.descriptionDate of Conference: 6-9 Nov. 2011en_US
dc.description.abstractPolar codes are a class of codes versatile enough to achieve the Shannon bound in a large array of source and channel coding problems. For that reason it is important to have efficient implementation architectures for polar codes in hardware. Motivated by this fact we propose a belief propagation (BP) decoder architecture for an increasingly popular hardware platform; Field Programmable Gate Array (FPGA). The proposed architecture supports any code rate and is quite flexible in terms of hardware complexity and throughput. The architecture can also be extended to support multiple block lengths without increasing the hardware complexity a lot. Moreover various schedulers can be adapted into the proposed architecture so that list decoding techniques can be used with a single block. Finally the proposed architecture is compared with a convolutional turbo code (CTC) decoder for WiMAX taken from a Xilinx Product Specification and seen that polar codes are superior to CTC codes both in hardware complexity and throughput. © 2011 IEEE.en_US
dc.description.provenanceMade available in DSpace on 2016-02-08T12:16:58Z (GMT). No. of bitstreams: 1 bilkent-research-paper.pdf: 70227 bytes, checksum: 26e812c6f5156f83f0e77b261a471b5a (MD5) Previous issue date: 2011en
dc.identifier.doi10.1109/ISWCS.2011.6125398en_US
dc.identifier.issn2154-0217
dc.identifier.urihttp://hdl.handle.net/11693/28305
dc.language.isoEnglishen_US
dc.publisherIEEEen_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/ISWCS.2011.6125398en_US
dc.source.title2011 8th International Symposium on Wireless Communication Systemsen_US
dc.subjectFPGAen_US
dc.subjectPolar codesen_US
dc.subjectBelief propagationen_US
dc.subjectBelief propagation decodingen_US
dc.subjectBlock lengthsen_US
dc.subjectBP decoderen_US
dc.subjectCode ratesen_US
dc.subjectConvolutional turbo codesen_US
dc.subjectDecoder architectureen_US
dc.subjectEfficient implementationen_US
dc.subjectFPGA implementationsen_US
dc.subjectHardware complexityen_US
dc.subjecthardware implementationen_US
dc.subjectHardware platformen_US
dc.subjectLarge arraysen_US
dc.subjectList decodingen_US
dc.subjectPolar codesen_US
dc.subjectProduct specificationsen_US
dc.subjectProposed architecturesen_US
dc.subjectShannon bounden_US
dc.subjectSource and channel codingen_US
dc.subjectDecodingen_US
dc.subjectField programmable gate arrays (FPGA)en_US
dc.subjectGlobal system for mobile communicationsen_US
dc.subjectHardwareen_US
dc.subjectSignal receiversen_US
dc.subjectWimaxen_US
dc.subjectArchitectureen_US
dc.titleAn FPGA implementation architecture for decoding of polar codesen_US
dc.typeConference Paperen_US

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