Two novel multiway circuit partitioning algorithms using relaxed locking

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buir.contributor.authorAykanat, Cevdet
dc.citation.epage178en_US
dc.citation.issueNumber2en_US
dc.citation.spage169en_US
dc.citation.volumeNumber16en_US
dc.contributor.authorDasdan, A.en_US
dc.contributor.authorAykanat, Cevdeten_US
dc.date.accessioned2016-02-08T10:46:59Z
dc.date.available2016-02-08T10:46:59Zen_US
dc.date.issued1997en_US
dc.departmentDepartment of Computer Engineeringen_US
dc.description.abstractAll the previous Kernighan-Lin-based (KL-based) circuit partitioning algorithms employ the locking mechanism, which enforces each cell to move exactly once per pass. In this paper, we propose two novel approaches for multiway circuit partitioning to overcome this limitation. Our approaches allow each cell to move more than once. Our first approach still uses the locking mechanism but in a relaxed way. It introduces the phase concept such that each pass can include more than one phase, and a phase can include at most one move of each cell. Our second approach does not use the locking mechanism at all. It introduces the mobility concept such that each cell can move as freely as allowed by its mobility. Each approach leads to KL-based generic algorithms whose parameters can be set to obtain algorithms with different performance characteristics. We generated three versions of each generic algorithm and evaluated them on a subset of common benchmark circuits in comparison with Sanchis' algorithm (FMS) and the simulated annealing algorithm (SA). Experimental results show that our algorithms are efficient, they outperform FMS significantly, and they perform comparably to SA. Our algorithms perform relatively better as the number of parts in the partition increases as well as the density of the circuit decreases. This paper also provides guidelines for good parameter settings for the generic algorithms. © 1997 IEEE.en_US
dc.identifier.doi10.1109/43.573831en_US
dc.identifier.eissn1937-4151
dc.identifier.issn0278-0070
dc.identifier.urihttp://hdl.handle.net/11693/25571en_US
dc.language.isoEnglishen_US
dc.publisherIEEEen_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/43.573831en_US
dc.source.titleIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systemsen_US
dc.subjectIterative Improvementen_US
dc.subjectKernighan-Lin-Based Algorithmsen_US
dc.subjectMove-Based Partitioningen_US
dc.subjectMultiway Circuit Partitioningen_US
dc.subjectRelaxed Lockingen_US
dc.subjectVery large scale integration (vlsi)en_US
dc.subjectComputer Aided Network Analysisen_US
dc.subjectGenetic Algorithmsen_US
dc.subjectIterative Methodsen_US
dc.subjectSimulated Annealingen_US
dc.subjectVLSI Circuitsen_US
dc.titleTwo novel multiway circuit partitioning algorithms using relaxed lockingen_US
dc.typeArticleen_US

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