An execution triggered coarse grained recongigurable architecture

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buir.advisorAtalar, Abdullah
dc.contributor.authorAtak, Oğuzhan
dc.date.accessioned2016-01-08T18:19:09Z
dc.date.available2016-01-08T18:19:09Z
dc.date.issued2012
dc.departmentDepartment of Electrical and Electronics Engineeringen_US
dc.descriptionAnkara : The Department of Electrical and Electronics Engineering and the Graduate School of Engineering and Science of Bilkent University, 2012.en_US
dc.descriptionThesis (Ph. D) -- Bilkent University, 2012.en_US
dc.descriptionIncludes bibliographical refences.en_US
dc.description.abstractIn this thesis, we present BilRC (Bilkent Reconfigurable Computer), a new coarse-grained reconfigurable architecture. The distinguishing feature of BilRC is its novel execution-triggering computation model which allows a broad range of applications to be efficiently implemented. In order to map applications onto BilRC, we developed a control data flow graph language, named LRC (a Language for Reconfigurable Computing). The flexibility of the architecture and the computation model are validated by mapping several real world applications. LRC is also used to map applications to a 90nm FPGA, giving exactly the same cycle count performance. It is found that BilRC reduces the configuration size about 33 times. It is synthesized with 90nm technology and typical applications mapped on BilRC run about 2.5 times faster than those on FPGA. It is found that the cycle counts of the applications for a commercial VLIW DSP processor are 1.9 to 15 times higher than that of BilRC. It is also found that BilRC can run the inverse discrete cosine transform algorithm almost 3 times faster than the closest CGRA in terms of cycle count. Although the area required for BilRC processing elements is larger than that of existing CGRAs, this is mainly due to the segmented interconnect architecture of BilRC, which is crucial for supporting a broad range of applications.en_US
dc.description.degreePh.D.en_US
dc.description.provenanceMade available in DSpace on 2016-01-08T18:19:09Z (GMT). No. of bitstreams: 1 0006215.pdf: 688739 bytes, checksum: ff3e6a85629e3e7070e63d6a73b5be82 (MD5)en
dc.description.statementofresponsibilityAtak, Oğuzhanen_US
dc.format.extentxv, 100 leaves, graphicsen_US
dc.identifier.urihttp://hdl.handle.net/11693/15478
dc.language.isoEnglishen_US
dc.publisherBilkent Universityen_US
dc.rightsinfo:eu-repo/semantics/openAccessen_US
dc.subjectCoarse-grained Reconfigurable Architectures (CGRA)en_US
dc.subjectDiscrete Cosine Transform (DCT)en_US
dc.subjectViterbi Decoderen_US
dc.subjectTurbo Decoderen_US
dc.subjectFast Fourier Transform (FFT)en_US
dc.subjectReconfigurable Computingen_US
dc.subjectField Programmable Gate Arrays (FPGA)en_US
dc.subject.lccQA76.9.A3 A83 2012en_US
dc.subject.lcshAdaptive computing systems.en_US
dc.subject.lcshFied programmable gate arrays.en_US
dc.titleAn execution triggered coarse grained recongigurable architectureen_US
dc.typeThesisen_US

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