Hardware implementation of fano decoder for polarization-adjusted convolutional (PAC) codes
buir.contributor.author | Mozammel, Amir | |
buir.contributor.orcid | Mozammel, Amir|0000-0003-3474-9530 | |
dc.contributor.author | Mozammel, Amir | |
dc.date.accessioned | 2022-01-28T11:02:00Z | |
dc.date.available | 2022-01-28T11:02:00Z | |
dc.date.issued | 2021-10-26 | |
dc.department | Department of Electrical and Electronics Engineering | en_US |
dc.description | ( Early Access ) | en_US |
dc.description.abstract | This brief proposes a hardware implementation architecture for Fano decoding of polarization-adjusted convolutional (PAC) codes. This architecture uses a novel branch metric unit specific to PAC codes. The proposed decoder is tested on FPGA, and its performance is evaluated on ASIC using TSMC 28 nm 0.72 V library. The decoder can be clocked at 500 MHz and reach an average information throughput of 38 Mb/s at 3.5 dB signal-to-noise ratio for a block length of 128 and a code rate of 1/2. | en_US |
dc.description.provenance | Submitted by Evrim Ergin (eergin@bilkent.edu.tr) on 2022-01-28T11:02:00Z No. of bitstreams: 1 Hardware_implementation_of_fano_decoder_for_polarization-adjusted_convolutional_(PAC)_codes.pdf: 831156 bytes, checksum: 0079f267eb1f618497ab95a71133bd96 (MD5) | en |
dc.description.provenance | Made available in DSpace on 2022-01-28T11:02:00Z (GMT). No. of bitstreams: 1 Hardware_implementation_of_fano_decoder_for_polarization-adjusted_convolutional_(PAC)_codes.pdf: 831156 bytes, checksum: 0079f267eb1f618497ab95a71133bd96 (MD5) Previous issue date: 2021-10-26 | en |
dc.identifier.doi | 10.1109/TCSII.2021.3123270 | en_US |
dc.identifier.eissn | 1558-3791 | |
dc.identifier.issn | 1549-7747 | |
dc.identifier.uri | http://hdl.handle.net/11693/76868 | |
dc.language.iso | English | en_US |
dc.publisher | IEEE | en_US |
dc.relation.isversionof | https://doi.org/10.1109/TCSII.2021.3123270 | en_US |
dc.source.title | IEEE Transactions on Circuits and Systems II: Express Briefs | en_US |
dc.subject | PAC codes | en_US |
dc.subject | Sequential decoding | en_US |
dc.subject | Fano | en_US |
dc.subject | Polar coding | en_US |
dc.subject | VLSI | en_US |
dc.title | Hardware implementation of fano decoder for polarization-adjusted convolutional (PAC) codes | en_US |
dc.type | Article | en_US |
Files
Original bundle
1 - 1 of 1
Loading...
- Name:
- Hardware_implementation_of_fano_decoder_for_polarization-adjusted_convolutional_(PAC)_codes.pdf
- Size:
- 811.68 KB
- Format:
- Adobe Portable Document Format
- Description:
License bundle
1 - 1 of 1
No Thumbnail Available
- Name:
- license.txt
- Size:
- 1.69 KB
- Format:
- Item-specific license agreed upon to submission
- Description: