Reliability-aware 3D chip multiprocessor design

Abstract

Ability to stack separate chips in a single package enables three-dimensional integrated circuits (3D ICs). Heterogeneous 3D ICs provide even better opportunities to reduce the power and increase the performance per unit area. An important issue in designing a heterogeneous 3D IC is reliability. To achieve this, one needs to select the data mapping and processor layout carefully. In this paper, we try to perform this mapping and processor layout effectively. Specifically, on a heterogeneous 3D CMP, we explore how applications can be mapped onto 3D ICs to maximize reliability. Our preliminary experimental evaluation indicates that the proposed technique generates promising results in both reliability and performance.