A heterogeneous memory organization with minimum energy consumption in 3D chip-multiprocessors

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dc.contributor.authorAsad, Arghavanen_US
dc.contributor.authorOnsori, Salmanen_US
dc.contributor.authorFathy, M.en_US
dc.contributor.authorJahed-Motlagh, M. R.en_US
dc.contributor.authorRaahemifar, K.en_US
dc.coverage.spatialVancouver, BC, Canada
dc.date.accessioned2018-04-12T11:41:21Z
dc.date.available2018-04-12T11:41:21Z
dc.date.issued2016-05en_US
dc.departmentDepartment of Computer Engineeringen_US
dc.descriptionDate of Conference: 15-18 May 2016
dc.descriptionConference name: IEEE Canadian Conference on Electrical and Computer Engineering (CCECE) 2016
dc.description.abstractMain memories play an important role in overall energy consumption of embedded systems. Using conventional memory technologies in future designs in nanoscale era cause a drastic increase in leakage power consumption and temperature-related problems. Emerging non-volatile memory (NVM) technologies offer many desirable characteristics such as near-zero leakage power, high density and non-volatility. They can significantly mitigate the issue of memory leakage power in future embedded chip-multiprocessor (eCMP) systems. However, they suffer from challenges such as limited write endurance and high write energy consumption which restrict them for adoption in modern memory systems. In this article, we propose a stacked hybrid memory system for 3D chip-multiprocessors to take advantages of both traditional and non-volatile memory technologies. For reaching this target, we present a convex optimization-based model that minimizes the system energy consumption while satisfy endurance constraint in order to design a reliable memory system. Experimental results show that the proposed method improves energy-delay product (EDP) and performance by about 44.8% and 13.8% on average respectively compared with the traditional memory design where single technology is used. © 2016 IEEE.en_US
dc.description.provenanceMade available in DSpace on 2018-04-12T11:41:21Z (GMT). No. of bitstreams: 1 bilkent-research-paper.pdf: 179475 bytes, checksum: ea0bedeb05ac9ccfb983c327e155f0c2 (MD5) Previous issue date: 2016en
dc.identifier.doi10.1109/CCECE.2016.7726817en_US
dc.identifier.urihttp://hdl.handle.net/11693/37481
dc.language.isoEnglishen_US
dc.publisherIEEEen_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/CCECE.2016.7726817en_US
dc.source.titleIEEE Canadian Conference on Electrical and Computer Engineering (CCECE) 2016en_US
dc.subjectConvex-optimization problemen_US
dc.subjectDark siliconen_US
dc.subjectEmbedded Chip-Multiprocessor (eCMP)en_US
dc.subjectHeterogeneous memory systemen_US
dc.subjectNon-Volatile Memory (NVM)en_US
dc.subjectAdaptive systemsen_US
dc.subjectConvex optimizationen_US
dc.subjectDigital storageen_US
dc.subjectEmbedded systemsen_US
dc.subjectEnergy utilizationen_US
dc.subjectMultiprocessing systemsen_US
dc.subjectNonvolatile storageen_US
dc.subjectOptimizationen_US
dc.subjectProduct designen_US
dc.subjectConvex optimization problemsen_US
dc.subjectDark siliconsen_US
dc.subjectEmbedded chipsen_US
dc.subjectHeterogeneous memoryen_US
dc.subjectNon-volatile memoryen_US
dc.subjectData storage equipmenten_US
dc.titleA heterogeneous memory organization with minimum energy consumption in 3D chip-multiprocessorsen_US
dc.typeConference Paperen_US

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