Fabrication of 100 nm pMOSFETS With Hybrid AFW / STM lithography
buir.contributor.orcid | Atalar, Abdullah|0000-0002-1903-1240 | |
dc.contributor.author | Soh, H. T. | en_US |
dc.contributor.author | Wilder, K. | en_US |
dc.contributor.author | Atalar, Abdullah | en_US |
dc.contributor.author | Quate, C. F. | en_US |
dc.coverage.spatial | Kyoto, Japan, Japan | en_US |
dc.date.accessioned | 2019-03-28T08:47:55Z | |
dc.date.available | 2019-03-28T08:47:55Z | |
dc.date.issued | 1997-06 | en_US |
dc.department | Department of Electrical and Electronics Engineering | en_US |
dc.description.abstract | Scanning probe lithography (SPL) is an emerging area of research in which the scanning tunneling microscope (STM) or atomic force microscope (AFM) is used to pattern nanometer-scale features. Four factors will dictate the viability of SPL as a patterning technology for the semiconductor industry: 1) resolution, 2) alignment accuracy, 3) reliability, and 4) throughput. We present a new SPL technique-a hybrid between the AFM and STMto address these issues. We demonstrate its capabilities and its compatibility with semiconductor processing by fabricating a pMOSFET with an effective channel length (L,ff) of 100 nm and report the device characteristics. | en_US |
dc.description.provenance | Submitted by Taner Korkmaz (tanerkorkmaz@bilkent.edu.tr) on 2019-03-28T08:47:55Z No. of bitstreams: 1 Fabrication_Of_100_nm_pMOSFETS_With_Hybrid_AFW_STM_Lithography.pdf: 344961 bytes, checksum: 295a01a04621acd702507ee9b3059eab (MD5) | en |
dc.description.provenance | Made available in DSpace on 2019-03-28T08:47:55Z (GMT). No. of bitstreams: 1 Fabrication_Of_100_nm_pMOSFETS_With_Hybrid_AFW_STM_Lithography.pdf: 344961 bytes, checksum: 295a01a04621acd702507ee9b3059eab (MD5) Previous issue date: 1997-06 | en |
dc.identifier.doi | 10.1109/VLSIT.1997.623732 | en_US |
dc.identifier.isbn | 4-930813-75-1 | |
dc.identifier.uri | http://hdl.handle.net/11693/50794 | |
dc.language.iso | English | en_US |
dc.publisher | IEEE | en_US |
dc.relation.isversionof | https://doi.org/10.1109/VLSIT.1997.623732 | en_US |
dc.source.title | 1997 Symposium on VLSI Technology | en_US |
dc.subject | Logic gates | en_US |
dc.subject | Lithography | en_US |
dc.subject | Resists | en_US |
dc.subject | MOSFET | en_US |
dc.subject | Surfaces | en_US |
dc.subject | Probes | en_US |
dc.subject | Microscopy | en_US |
dc.title | Fabrication of 100 nm pMOSFETS With Hybrid AFW / STM lithography | en_US |
dc.type | Conference Paper | en_US |
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