Fabrication of 100 nm pMOSFETS With Hybrid AFW / STM lithography

buir.contributor.orcidAtalar, Abdullah|0000-0002-1903-1240
dc.contributor.authorSoh, H. T.en_US
dc.contributor.authorWilder, K.en_US
dc.contributor.authorAtalar, Abdullahen_US
dc.contributor.authorQuate, C. F.en_US
dc.coverage.spatialKyoto, Japan, Japanen_US
dc.date.accessioned2019-03-28T08:47:55Z
dc.date.available2019-03-28T08:47:55Z
dc.date.issued1997-06en_US
dc.departmentDepartment of Electrical and Electronics Engineeringen_US
dc.description.abstractScanning probe lithography (SPL) is an emerging area of research in which the scanning tunneling microscope (STM) or atomic force microscope (AFM) is used to pattern nanometer-scale features. Four factors will dictate the viability of SPL as a patterning technology for the semiconductor industry: 1) resolution, 2) alignment accuracy, 3) reliability, and 4) throughput. We present a new SPL technique-a hybrid between the AFM and STMto address these issues. We demonstrate its capabilities and its compatibility with semiconductor processing by fabricating a pMOSFET with an effective channel length (L,ff) of 100 nm and report the device characteristics.en_US
dc.description.provenanceSubmitted by Taner Korkmaz (tanerkorkmaz@bilkent.edu.tr) on 2019-03-28T08:47:55Z No. of bitstreams: 1 Fabrication_Of_100_nm_pMOSFETS_With_Hybrid_AFW_STM_Lithography.pdf: 344961 bytes, checksum: 295a01a04621acd702507ee9b3059eab (MD5)en
dc.description.provenanceMade available in DSpace on 2019-03-28T08:47:55Z (GMT). No. of bitstreams: 1 Fabrication_Of_100_nm_pMOSFETS_With_Hybrid_AFW_STM_Lithography.pdf: 344961 bytes, checksum: 295a01a04621acd702507ee9b3059eab (MD5) Previous issue date: 1997-06en
dc.identifier.doi10.1109/VLSIT.1997.623732en_US
dc.identifier.isbn4-930813-75-1
dc.identifier.urihttp://hdl.handle.net/11693/50794
dc.language.isoEnglishen_US
dc.publisherIEEEen_US
dc.relation.isversionofhttps://doi.org/10.1109/VLSIT.1997.623732en_US
dc.source.title1997 Symposium on VLSI Technologyen_US
dc.subjectLogic gatesen_US
dc.subjectLithographyen_US
dc.subjectResistsen_US
dc.subjectMOSFETen_US
dc.subjectSurfacesen_US
dc.subjectProbesen_US
dc.subjectMicroscopyen_US
dc.titleFabrication of 100 nm pMOSFETS With Hybrid AFW / STM lithographyen_US
dc.typeConference Paperen_US

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