High level synthesis based FPGA implementation of Matricized Tensor Times Khatri-Rao Product to accelerate canonical polyadic decomposition

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buir.advisorAykanat, Cevdet
dc.contributor.authorDoğu, Z. Saygın
dc.date.accessioned2019-12-06T11:19:00Z
dc.date.available2019-12-06T11:19:00Z
dc.date.copyright2019-10
dc.date.issued2019-10
dc.date.submitted2019-12-05
dc.descriptionCataloged from PDF version of article.en_US
dc.descriptionThesis (M.S.): Bilkent University, Department of Computer Engineering, İhsan Doğramacı Bilkent University, 2019.en_US
dc.descriptionIncludes bibliographical references (leaves 43-48).en_US
dc.description.abstractTensor factorization has many applications such as network anomaly detection, structural damage detection and music genre classification. Most time consuming part of the CPD-ALS based tensor factorization is the Matricized Tensor Times Khatri-Rao Product (MTTKRP). In this thesis, the goal was to show that an FPGA implementation of the MTTKRP kernel can be comparable with the state of the art software implementations. To achieve this goal, a flat design consisting of a single loop is developed using Vivado HLS. In order to process the large tensors with the limited BRAM capacity of the FPGA board, a tiling methodology with optimized processing order is introduced. It has been shown that tiling has a negative impact on the general performance because of increasing DRAM access per subtensor. On the other hand, with the minimum tiling possible to process the tensors, the FPGA implementation achieves up to 3.40 speedup against the single threaded software.en_US
dc.description.provenanceSubmitted by Betül Özen (ozen@bilkent.edu.tr) on 2019-12-06T11:19:00Z No. of bitstreams: 1 High_Level_Synthesis_Based_FPGA_Implementation_of_Matricized_Tensor_Times_Khatri_Rao_Product_to_Accelerate_Canonical_Polyadic_Decomposition.pdf: 1209242 bytes, checksum: 9727928b882122b155862d3108303be7 (MD5)en
dc.description.provenanceMade available in DSpace on 2019-12-06T11:19:00Z (GMT). No. of bitstreams: 1 High_Level_Synthesis_Based_FPGA_Implementation_of_Matricized_Tensor_Times_Khatri_Rao_Product_to_Accelerate_Canonical_Polyadic_Decomposition.pdf: 1209242 bytes, checksum: 9727928b882122b155862d3108303be7 (MD5) Previous issue date: 2019-10en
dc.description.statementofresponsibilityby Z. Saygın Doğuen_US
dc.format.extentxii, 48 leaves : charts (some color) ; 30 cm.en_US
dc.identifier.itemidB122003
dc.identifier.urihttp://hdl.handle.net/11693/52747
dc.language.isoEnglishen_US
dc.rightsinfo:eu-repo/semantics/openAccessen_US
dc.subjectFPGAen_US
dc.subjectHLSen_US
dc.subjectMTTRKPen_US
dc.subjectTensor factorizationen_US
dc.subjectCP decompositionen_US
dc.titleHigh level synthesis based FPGA implementation of Matricized Tensor Times Khatri-Rao Product to accelerate canonical polyadic decompositionen_US
dc.title.alternativeCanonical polyadic decomposition’ları hızlandırmak için matrisleştirilmiş tensör ile Khatri-Rao çarpımı’nın yüksek düzeyli sentezleme tabanlı FPGA implementasyonuen_US
dc.typeThesisen_US
thesis.degree.disciplineComputer Engineering
thesis.degree.grantorBilkent University
thesis.degree.levelMaster's
thesis.degree.nameMS (Master of Science)

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