Temperature-aware core mapping for heterogeneous 3D NoC design through constraint programming

buir.contributor.authorAhangari, Hamzeh
buir.contributor.authorÖztürk, Özcan
dc.citation.epage318en_US
dc.citation.spage312en_US
dc.contributor.authorDemiriz, A.en_US
dc.contributor.authorAhangari, Hamzehen_US
dc.contributor.authorÖztürk, Özcanen_US
dc.coverage.spatialVasteras, Swedenen_US
dc.date.accessioned2021-03-03T11:37:00Z
dc.date.available2021-03-03T11:37:00Z
dc.date.issued2020
dc.departmentDepartment of Computer Engineeringen_US
dc.descriptionDate of Conference: 11-13 March 2020en_US
dc.descriptionConference Name: 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2020en_US
dc.description.abstractIn the context of Network-on-Chip (NoC) based Chip Multiprocessor (CMP) design, core mapping for application specific systems is a challenging problem. In such designs, various decisions have to be made that affect performance and power consumption. Moreover, in emerging 3D NoC systems, by intensification of cooling issues, temperature constraints on hot-spots are added, and problem becomes more complicated. In this paper, an earlier Constraint Programming (CP) methodology for heterogeneous 2D NoC design is extended to 3D model, while critical temperature constraints are accounted. In a single-stage, our approach can choose core types from a set of low, medium and high power, and assign them to appropriate places on the mesh which minimizes the overall computation time and communication cost while satisfying the temperature constraints. To achieve our objective, in addition to cores placement problem, tasks should also be scheduled on corresponding cores with matching performance levels to minimize the overall completion time (makespan). Experimental results show that task completion times are more dependent on the mesh structure for our benchmark data. 3D mesh structures may yield shorter task completion times, without compromising thermal constraints. On the other hand, restricting the peak temperature naturally requires the usage of low-performance computing elements which inherently may delay the processing time.en_US
dc.description.provenanceSubmitted by Zeynep Aykut (zeynepay@bilkent.edu.tr) on 2021-03-03T11:37:00Z No. of bitstreams: 1 Temperature_aware_core_mapping_for_heterogeneous_3D_NoC_design_through_constraint_programming.pdf: 154433 bytes, checksum: c29ff0365d3eb4b569a2f5ee53689538 (MD5)en
dc.description.provenanceMade available in DSpace on 2021-03-03T11:37:00Z (GMT). No. of bitstreams: 1 Temperature_aware_core_mapping_for_heterogeneous_3D_NoC_design_through_constraint_programming.pdf: 154433 bytes, checksum: c29ff0365d3eb4b569a2f5ee53689538 (MD5) Previous issue date: 2020en
dc.identifier.doi10.1109/PDP50117.2020.00054en_US
dc.identifier.eisbn9781728165820en_US
dc.identifier.eissn2377-5750en_US
dc.identifier.isbn9781728165837en_US
dc.identifier.issn1066-6192en_US
dc.identifier.urihttp://hdl.handle.net/11693/75717en_US
dc.language.isoEnglishen_US
dc.publisherInstitute of Electrical and Electronics Engineersen_US
dc.relation.isversionofhttps://dx.doi.org/10.1109/PDP50117.2020.00054en_US
dc.source.titleProceedings of the 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2020en_US
dc.subjectNetwork-on-chipen_US
dc.subject3D integrationen_US
dc.subjectHeterogeneousen_US
dc.subjectCore mappingen_US
dc.subjectTask schedulingen_US
dc.subjectConstraint programmingen_US
dc.titleTemperature-aware core mapping for heterogeneous 3D NoC design through constraint programmingen_US
dc.typeConference Paperen_US

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