On-chip memory space partitioning for chip multiprocessors using polyhedral algebra

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dc.citation.epage498en_US
dc.citation.issueNumber6en_US
dc.citation.spage484en_US
dc.citation.volumeNumber4en_US
dc.contributor.authorOzturk, O.en_US
dc.contributor.authorKandemir, M.en_US
dc.contributor.authorIrwin, M. J.en_US
dc.date.accessioned2016-02-08T09:56:13Z
dc.date.available2016-02-08T09:56:13Z
dc.date.issued2010en_US
dc.departmentDepartment of Computer Engineeringen_US
dc.description.abstractOne of the most important issues in designing a chip multiprocessor is to decide its on-chip memory organisation. While it is possible to design an application-specific memory architecture, this may not necessarily be the best option, in particular when storage demands of individual processors and/or their data sharing patterns can change from one point in execution to another for the same application. Here, two problems are formulated. First, we show how a polyhedral method can be used to design, for array-based data-intensive embedded applications, an application-specific hybrid memory architecture that has both shared and private components. We evaluate the resulting memory configurations using a set of benchmarks and compare them to pure private and pure shared memory on-chip multiprocessor architectures. The second approach proposed consider dynamic configuration of software-managed on-chip memory space to adapt to the runtime variations in data storage demand and interprocessor sharing patterns. The proposed framework is fully implemented using an optimising compiler, a polyhedral tool, and a memory partitioner (based on integer linear programming), and is tested using a suite of eight data-intensive embedded applications. © 2010 © The Institution of Engineering and Technology.en_US
dc.identifier.doi10.1049/iet-cdt.2009.0089en_US
dc.identifier.issn1751-8601
dc.identifier.urihttp://hdl.handle.net/11693/22152
dc.language.isoEnglishen_US
dc.publisherThe Institution of Engineering and Technologyen_US
dc.relation.isversionofhttp://dx.doi.org/10.1049/iet-cdt.2009.0089en_US
dc.source.titleIET Computers and Digital Techniquesen_US
dc.subjectApplication-specificen_US
dc.subjectChip multiprocessoren_US
dc.subjectData sharingen_US
dc.subjectData storageen_US
dc.subjectDynamic configurationen_US
dc.subjectEmbedded applicationen_US
dc.subjectHybrid memoriesen_US
dc.subjectInteger linear programmingen_US
dc.subjectInterprocessor sharingen_US
dc.subjectMemory architectureen_US
dc.subjectMemory configurationen_US
dc.subjectOn chip memoryen_US
dc.subjectOn-chip multiprocessoren_US
dc.subjectRun-time variationsen_US
dc.subjectShared memoriesen_US
dc.subjectInteger programmingen_US
dc.subjectMicroprocessor chipsen_US
dc.subjectMultiprocessing systemsen_US
dc.subjectOptimizationen_US
dc.subjectSystems analysisen_US
dc.subjectComputer architectureen_US
dc.titleOn-chip memory space partitioning for chip multiprocessors using polyhedral algebraen_US
dc.typeArticleen_US

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