OpenCL-based efficient HLS implementation of iterative graph algorithms on FPGA

The emergence of CPU-FPGA hybrid architectures creates a demand for high abstraction programming tools such as High-Level Synthesis (HLS). HLS handles most of the FPGA development tasks automatically, thus freeing up programmers to create applications effortlessly on FPGAs with familiar programming languages. However, HLS often trades speed for convenience, which makes it a poor choice when it comes to applications in which computational performance is a crucial requirement, such as graph algorithms. In the scope of iterative graph algorithms, we developed custom HLS-based optimizations. Specifically, we applied these on PageRank (PR), Breadth-First Search (BFS), and Connected Components (CC) algorithms so that they can be synthesized in a performant way by HLS tools. We observed that well-pipelined OpenCL kernels can provide up to three times speedups on the Intel Xeon-FPGA architecture compared to CPU implementations. We optimized the traversal of vertices for pipelining to execute applications faster. Furthermore, our approach relies on the HLS workflow to make it effortless for the programmer.