A template-based design methodology for graph-parallel hardware accelerators

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buir.contributor.authorYeşil, Şerif
buir.contributor.authorÖzdal, Muhammet Mustafa
dc.citation.epage430en_US
dc.citation.issueNumber2en_US
dc.citation.spage420en_US
dc.citation.volumeNumber37en_US
dc.contributor.authorAyupov, A.en_US
dc.contributor.authorYeşil, Şerifen_US
dc.contributor.authorÖzdal, Muhammet Mustafaen_US
dc.contributor.authorKim, T.en_US
dc.contributor.authorBurns, S.en_US
dc.contributor.authorÖztürk, Özcanen_US
dc.date.accessioned2018-05-07T10:34:59Z
dc.date.available2018-05-07T10:34:59Z
dc.date.issued2017-05en_US
dc.departmentDepartment of Computer Engineeringen_US
dc.description.abstractGraph applications have been gaining importance in the last decade due to emerging big data analytics problems such as Web graphs, social networks, and biological networks. For these applications, traditional CPU and GPU architectures suffer in terms of performance and power consumption due to irregular communications, random memory accesses, and load balancing problems. It has been shown that specialized hardware accelerators can achieve much better power and energy efficiency compared to the general purpose CPUs and GPUs. In this paper, we present a template-based methodology specifically targeted for hardware accelerator design of big-data graph applications. Important architectural features that are key for energy efficient execution are implemented in a common template. The proposed template-based methodology is used to design hardware accelerators for different graph applications with little effort. Compared to an application-specific high-level synthesis methodology, we show that the proposed methodology can generate hardware accelerators with up to 18× better energy efficiency and requires less design effort.en_US
dc.identifier.doi10.1109/TCAD.2017.2706562en_US
dc.identifier.issn0278-0070
dc.identifier.urihttp://hdl.handle.net/11693/46922
dc.language.isoEnglishen_US
dc.publisherIEEEen_US
dc.relationinfo:eu-repo/grantAgreement/EC/H2020/704476/en_US
dc.relation.isversionofhttps://doi.org/10.1109/TCAD.2017.2706562en_US
dc.relation.projectEnergy Efficient FPGA Accelerators for Graph Analytics Applicationsen_US
dc.rightsinfo:eu-repo/semantics/openAccess*
dc.source.titleIEEE Council on Electronic Design Automationen_US
dc.subjectAccelerationen_US
dc.subjectBig dataen_US
dc.subjectHardwareen_US
dc.subjectHigh level synthesisen_US
dc.subjectProgram processorsen_US
dc.titleA template-based design methodology for graph-parallel hardware acceleratorsen_US
dc.typeArticleen_US

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