Controller design for delay margin improvement
buir.contributor.author | Özbay, Hitay | |
dc.citation.epage | 2914 | en_US |
dc.citation.spage | 2910 | en_US |
dc.contributor.author | Gündeş, A. N. | en_US |
dc.contributor.author | Özbay, Hitay | en_US |
dc.coverage.spatial | Naples, Italy | en_US |
dc.date.accessioned | 2020-01-24T05:42:11Z | |
dc.date.available | 2020-01-24T05:42:11Z | |
dc.date.issued | 2019 | |
dc.department | Department of Electrical and Electronics Engineering | en_US |
dc.description | Date of Conference: 25-28 June 2019 | en_US |
dc.description | Conference name: Control Conference (ECC), European | en_US |
dc.description.abstract | Two important design objectives in feedback control are steady-state error minimization and delay margin maximization. In general these two objectives work against each other. This paper starts with an initial controller designed to satisfy the steady-state error requirement, and shows how one can modify it to improve the delay margin without changing the steady-state error | en_US |
dc.description.provenance | Submitted by Onur Emek (onur.emek@bilkent.edu.tr) on 2020-01-24T05:42:11Z No. of bitstreams: 1 Controller_design_for_delay_margin_improvement.pdf: 329621 bytes, checksum: 16b00a3d8344acf1eadcb8c82e02472f (MD5) | en |
dc.description.provenance | Made available in DSpace on 2020-01-24T05:42:11Z (GMT). No. of bitstreams: 1 Controller_design_for_delay_margin_improvement.pdf: 329621 bytes, checksum: 16b00a3d8344acf1eadcb8c82e02472f (MD5) Previous issue date: 2019 | en |
dc.identifier.doi | 10.23919/ECC.2019.8796063 | en_US |
dc.identifier.isbn | 9783907144008 | |
dc.identifier.uri | http://hdl.handle.net/11693/52787 | |
dc.language.iso | English | en_US |
dc.publisher | IEEE | en_US |
dc.relation.isversionof | https://dx.doi.org/10.23919/ECC.2019.8796063 | en_US |
dc.source.title | 2019 18th European Control Conference (ECC) | en_US |
dc.title | Controller design for delay margin improvement | en_US |
dc.type | Conference Paper | en_US |
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