Controller design for delay margin improvement

buir.contributor.authorÖzbay, Hitay
dc.citation.epage2914en_US
dc.citation.spage2910en_US
dc.contributor.authorGündeş, A. N.en_US
dc.contributor.authorÖzbay, Hitayen_US
dc.coverage.spatialNaples, Italyen_US
dc.date.accessioned2020-01-24T05:42:11Z
dc.date.available2020-01-24T05:42:11Z
dc.date.issued2019
dc.departmentDepartment of Electrical and Electronics Engineeringen_US
dc.descriptionDate of Conference: 25-28 June 2019en_US
dc.descriptionConference name: Control Conference (ECC), Europeanen_US
dc.description.abstractTwo important design objectives in feedback control are steady-state error minimization and delay margin maximization. In general these two objectives work against each other. This paper starts with an initial controller designed to satisfy the steady-state error requirement, and shows how one can modify it to improve the delay margin without changing the steady-state erroren_US
dc.description.provenanceSubmitted by Onur Emek (onur.emek@bilkent.edu.tr) on 2020-01-24T05:42:11Z No. of bitstreams: 1 Controller_design_for_delay_margin_improvement.pdf: 329621 bytes, checksum: 16b00a3d8344acf1eadcb8c82e02472f (MD5)en
dc.description.provenanceMade available in DSpace on 2020-01-24T05:42:11Z (GMT). No. of bitstreams: 1 Controller_design_for_delay_margin_improvement.pdf: 329621 bytes, checksum: 16b00a3d8344acf1eadcb8c82e02472f (MD5) Previous issue date: 2019en
dc.identifier.doi10.23919/ECC.2019.8796063en_US
dc.identifier.isbn9783907144008
dc.identifier.urihttp://hdl.handle.net/11693/52787
dc.language.isoEnglishen_US
dc.publisherIEEEen_US
dc.relation.isversionofhttps://dx.doi.org/10.23919/ECC.2019.8796063en_US
dc.source.title2019 18th European Control Conference (ECC)en_US
dc.titleController design for delay margin improvementen_US
dc.typeConference Paperen_US

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