BilRC: an execution triggered coarse grained reconfigurable architecture

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buir.contributor.orcidAtalar, Abdullah|0000-0002-1903-1240
dc.citation.epage1298en_US
dc.citation.issueNumber7en_US
dc.citation.spage1285en_US
dc.citation.volumeNumber21en_US
dc.contributor.authorAtak, O.en_US
dc.contributor.authorAtalar, Abdullahen_US
dc.date.accessioned2015-07-28T12:05:22Z
dc.date.available2015-07-28T12:05:22Z
dc.date.issued2013-07en_US
dc.departmentDepartment of Electrical and Electronics Engineeringen_US
dc.description.abstractWe present Bilkent reconfigurable computer (BilRC), a new coarse-grained reconfigurable architecture (CGRA) employing an execution-triggering mechanism. A control data flow graph language is presented for mapping the applications to BilRC. The flexibility of the architecture and the computation model are validated by mapping several real-world applications. The same language is also used to map applications to a 90-nm field-programmable gate array (FPGA), giving exactly the same cycle count performance. It is found that BilRC reduces the configuration size about 33 times. It is synthesized with 90-nm technology, and typical applications mapped on BilRC run about 2.5 times faster than those on FPGA. It is found that the cycle counts of the applications for a commercial very long instruction word digital signal processor processor are 1.9 to 15 times higher than that of BilRC. It is also found that BilRC can run the inverse discrete cosine transform algorithm almost 3 times faster than the closest CGRA in terms of cycle count. Although the area required for BilRC processing elements is larger than that of existing CGRAs, this is mainly due to the segmented interconnect architecture of BilRC, which is crucial for supporting a broad range of applications.en_US
dc.description.provenanceMade available in DSpace on 2015-07-28T12:05:22Z (GMT). No. of bitstreams: 1 10.1109-TVLSI.2012.2207748.pdf: 1275425 bytes, checksum: 4f2978818fba7cad81a88c46260389c6 (MD5)en
dc.identifier.doi10.1109/TVLSI.2012.2207748en_US
dc.identifier.issn1063-8210
dc.identifier.urihttp://hdl.handle.net/11693/13247
dc.language.isoEnglishen_US
dc.publisherIEEEen_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/TVLSI.2012.2207748en_US
dc.source.titleIEEE Transactions on Very Large Scale Integration (VLSI) Systemsen_US
dc.subjectCoarse-grained Reconfigurable Architectures (cgra)en_US
dc.subjectDiscrete Cosine Transform (dct)en_US
dc.subjectFast Fourier Transform (fft)en_US
dc.subjectReconfigurable Computingen_US
dc.subjectTurbo Decoderen_US
dc.subjectViterbi Decoderen_US
dc.titleBilRC: an execution triggered coarse grained reconfigurable architectureen_US
dc.typeArticleen_US

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