Optimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchy

dc.citation.epage98en_US
dc.citation.spage76en_US
dc.citation.volumeNumber51en_US
dc.contributor.authorAsad, A.en_US
dc.contributor.authorOzturk, O.en_US
dc.contributor.authorFathy, M.en_US
dc.contributor.authorJahed-Motlagh, M. R.en_US
dc.date.accessioned2018-04-12T11:11:12Z
dc.date.available2018-04-12T11:11:12Z
dc.date.issued2017en_US
dc.departmentDepartment of Computer Engineeringen_US
dc.description.abstractManagement of a problem recently known as “dark silicon” is a new challenge in multicore designs. Prior innovative studies have addressed the dark silicon problem in the fields of power-efficient core design. However, addressing dark silicon challenges in uncore component designs such as cache hierarchy, on-chip interconnect etc. that consume significant portion of the on-chip power consumption is largely unexplored. In this paper, for the first time, we propose an integrated approach which considers the impact of power consumption of core and uncore components simultaneously to improve multi/many-core performance in the dark silicon era. The proposed approach dynamically (1) predicts the changing program behavior on each core; (2) re-determines frequency/voltage, cache capacity and technology in each level of the cache hierarchy based on the program's scalability in order to satisfy the power and temperature constraints. In the proposed architecture, for future chip-multiprocessors (CMPs), we exploit emerging technologies such as non-volatile memories (NVMs) and 3D techniques to combat dark silicon. Also, for the first time, we propose a detailed power model which is useful for future dark silicon CMPs power modeling. Experimental results on SPEC 2000/2006 benchmarks show that the proposed method improves throughput by about 54.3% and energy-delay product by about 61% on average, respectively, in comparison with the conventional CMP architecture with homogenous cache system. (A preliminary short version of this work was presented in the 18th Euromicro Conference on Digital System Design (DSD), 2015.) © 2017 Elsevier B.V.en_US
dc.description.provenanceMade available in DSpace on 2018-04-12T11:11:12Z (GMT). No. of bitstreams: 1 bilkent-research-paper.pdf: 179475 bytes, checksum: ea0bedeb05ac9ccfb983c327e155f0c2 (MD5) Previous issue date: 2017en
dc.embargo.release2019-06-01en_US
dc.identifier.doi10.1016/j.micpro.2017.03.011en_US
dc.identifier.issn0141-9331en_US
dc.identifier.urihttp://hdl.handle.net/11693/37356en_US
dc.language.isoEnglishen_US
dc.publisherElsevier BVen_US
dc.relation.isversionofhttp://dx.doi.org/10.1016/j.micpro.2017.03.011en_US
dc.source.titleMicroprocessors and Microsystemsen_US
dc.subjectChip-multiprocessor (CMP)en_US
dc.subjectDark-siliconen_US
dc.subjectHybrid cache hierarchyen_US
dc.subjectNetwork-on-chip (NoC)en_US
dc.subjectNon-volatile memory (NVM)en_US
dc.subjectOptimizationen_US
dc.subjectReconfigurable cacheen_US
dc.subjectAdaptive systemsen_US
dc.subjectCache memoryen_US
dc.subjectData storage equipmenten_US
dc.subjectDigital storageen_US
dc.subjectElectric power utilizationen_US
dc.subjectMultiprocessing systemsen_US
dc.subjectNetwork architectureen_US
dc.subjectNetwork-on-chipen_US
dc.subjectSiliconen_US
dc.subjectSystems analysisen_US
dc.subjectThree dimensional integrated circuitsen_US
dc.subjectChip multiprocessorsen_US
dc.subjectHybrid cachesen_US
dc.subjectReconfigurableen_US
dc.subjectIntegrated circuit designen_US
dc.titleOptimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchyen_US
dc.typeArticleen_US

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