Hybrid stacked memory architecture for energy efficient embedded chip-multiprocessors based on compiler directed approach

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dc.citation.epage7en_US
dc.citation.spage1en_US
dc.contributor.authorOnsori, Salmanen_US
dc.contributor.authorAsad, A.en_US
dc.contributor.authorÖztürk, Özcanen_US
dc.contributor.authorFathy, M.en_US
dc.coverage.spatialLas Vegas, NV, USA
dc.date.accessioned2018-04-12T11:49:25Z
dc.date.available2018-04-12T11:49:25Z
dc.date.issued2015-12en_US
dc.departmentDepartment of Computer Engineeringen_US
dc.descriptionDate of Conference: 14-16 Dec. 2015
dc.descriptionConference name: Sixth International Green and Sustainable Computing Conference, (IGSC) 2015
dc.description.abstractEnergy consumption becomes the most critical limitation on the performance of nowadays embedded system designs. On-chip memories due to major contribution in overall system energy consumption are always significant issue for embedded systems. Using conventional memory technologies in future designs in nano-scale era causes a drastic increase in leakage power consumption and temperature-related problems. Emerging non-volatile memory (NVM) technologies are promising replacement for conventional memory structure in embedded systems due to its attractive characteristics such as near-zero leakage power, high density and non-volatility. Recent advantages of NVM technologies can significantly mitigate the issue of memory leakage power. However, they introduce new challenges such as limited write endurance and high write energy consumption which restrict them for adoption in modern memory systems. In this article, we propose a stacked hybrid memory system to minimize energy consumption for 3D embedded chip-multiprocessors (eCMP). For reaching this target, we present a convex optimization-based model to distribute data blocks between SRAM and NVM banks based on data access pattern derived by compiler. Our compiler-assisted hybrid memory architecture can achieve up to 51.28 times improvement in lifetime. In addition, experimental results show that our proposed method reduce energy consumption by 56% on average compared to the traditional memory design where single technology is used. © 2015 IEEE.en_US
dc.description.provenanceMade available in DSpace on 2018-04-12T11:49:25Z (GMT). No. of bitstreams: 1 bilkent-research-paper.pdf: 179475 bytes, checksum: ea0bedeb05ac9ccfb983c327e155f0c2 (MD5) Previous issue date: 2016en
dc.identifier.doi10.1109/IGCC.2015.7393714en_US
dc.identifier.urihttp://hdl.handle.net/11693/37730
dc.language.isoEnglishen_US
dc.publisherIEEEen_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/IGCC.2015.7393714en_US
dc.source.title6th International Green and Sustainable Computing Conference, (IGSC) 2015en_US
dc.subjectCompiler-assisteden_US
dc.subjectConvex-optimization based modelen_US
dc.subjectEmbedded chip-multiprocessor (eCMP)en_US
dc.subjectHybrid memory architectureen_US
dc.subjectNon-volatile memory (NVM)en_US
dc.subjectAdaptive systemsen_US
dc.subjectConvex optimizationen_US
dc.subjectData storage equipmenten_US
dc.subjectDigital storageen_US
dc.subjectEmbedded systemsen_US
dc.subjectEnergy efficiencyen_US
dc.subjectEnergy utilizationen_US
dc.subjectMultiprocessing systemsen_US
dc.subjectNanotechnologyen_US
dc.subjectNonvolatile storageen_US
dc.subjectProgram compilersen_US
dc.subjectStatic random access storageen_US
dc.subjectSystems analysisen_US
dc.subjectData access patternsen_US
dc.subjectEmbedded chipsen_US
dc.subjectEmerging non-volatile memoryen_US
dc.subjectLeakage power consumptionen_US
dc.subjectReduce energy consumptionen_US
dc.subjectSystem energy consumptionen_US
dc.subjectMemory architectureen_US
dc.titleHybrid stacked memory architecture for energy efficient embedded chip-multiprocessors based on compiler directed approachen_US
dc.typeConference Paperen_US

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