Test case verification by model checking
dc.citation.epage | 321 | en_US |
dc.citation.issueNumber | 3 | en_US |
dc.citation.spage | 277 | en_US |
dc.citation.volumeNumber | 2 | en_US |
dc.contributor.author | Naik, K. | en_US |
dc.contributor.author | Sarikaya, B. | en_US |
dc.date.accessioned | 2016-02-08T10:54:09Z | |
dc.date.available | 2016-02-08T10:54:09Z | |
dc.date.issued | 1993 | en_US |
dc.department | Department of Computer Engineering | en_US |
dc.description.abstract | Verification of a test case for testing the conformance of protocol implementations against the formal description of the protocol involves verifying three aspects of the test case: expected input/output test behavior, test verdicts, and the test purpose. We model the safety and liveness properties of a test case using branching time temporal logic. There are four types of safety properties: transmission safety, reception safety, synchronization safety, and verdict safety. We model a test purpose as a liveness property and give a set of notations to formally specify a test purpose. All these properties expressed as temporal formulas are verified using model checking on an extended state machine graph representing the composed behavior of a test case and protocol specification. This methodology is shown to be effective in finding errors in manually developed conformance test suites. © 1993 Kluwer Academic Publishers. | en_US |
dc.description.provenance | Made available in DSpace on 2016-02-08T10:54:09Z (GMT). No. of bitstreams: 1 bilkent-research-paper.pdf: 70227 bytes, checksum: 26e812c6f5156f83f0e77b261a471b5a (MD5) Previous issue date: 1993 | en |
dc.identifier.doi | 10.1007/BF01384135 | en_US |
dc.identifier.issn | 0925-9856 | |
dc.identifier.uri | http://hdl.handle.net/11693/26042 | |
dc.language.iso | English | en_US |
dc.publisher | Kluwer Academic Publishers | en_US |
dc.relation.isversionof | http://dx.doi.org/10.1007/BF01384135 | en_US |
dc.source.title | Formal Methods in System Design | en_US |
dc.subject | Estelle | en_US |
dc.subject | extended finite-state machines | en_US |
dc.subject | liveness properties | en_US |
dc.subject | model checking | en_US |
dc.subject | reachability analysis | en_US |
dc.subject | safety properties | en_US |
dc.subject | temporal logic | en_US |
dc.subject | TTCN | en_US |
dc.subject | Computer hardware description languages | en_US |
dc.subject | Computer testing | en_US |
dc.subject | Data communication systems | en_US |
dc.subject | Finite automata | en_US |
dc.subject | Mathematical models | en_US |
dc.subject | Synchronization | en_US |
dc.subject | Systems analysis | en_US |
dc.subject | Extended finite state machines | en_US |
dc.subject | Liveness properties | en_US |
dc.subject | Model checking | en_US |
dc.subject | Reachability analysis | en_US |
dc.subject | Safety properties | en_US |
dc.subject | Temporal logic | en_US |
dc.subject | Network protocols | en_US |
dc.title | Test case verification by model checking | en_US |
dc.type | Article | en_US |
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