Optimal linewidth distribution minimizing average signal delay for RC limited circuits
buir.contributor.author | Haldun M. Özaktaş | |
dc.citation.epage | 410 | en_US |
dc.citation.issueNumber | 3 | en_US |
dc.citation.spage | 407 | en_US |
dc.citation.volumeNumber | 74 | en_US |
dc.contributor.author | Özaktaş, Haldun M. | |
dc.contributor.author | Goodman, J. W. | |
dc.date.accessioned | 2016-02-08T10:54:21Z | |
dc.date.available | 2016-02-08T10:54:21Z | |
dc.date.issued | 1993 | en_US |
dc.department | Department of Electrical and Electronics Engineering | en_US |
dc.description.abstract | Based on idealized interconnect scaling rules, we derive the optimal distribution of linewidths as a function of length for wire-limited layouts utilizing RC-limited interconnections. We show that the width of the wires should be chosen proportional to the cube root of their length for two-dimensional layouts and proportional to the fourth root of their length for full three-dimensional layouts so as to minimize average signal delay. | en_US |
dc.description.provenance | Made available in DSpace on 2016-02-08T10:54:21Z (GMT). No. of bitstreams: 1 bilkent-research-paper.pdf: 70227 bytes, checksum: 26e812c6f5156f83f0e77b261a471b5a (MD5) Previous issue date: 1993 | en |
dc.identifier.doi | 10.1080/00207219308925844 | en_US |
dc.identifier.issn | 0020-7217 | |
dc.identifier.uri | http://hdl.handle.net/11693/26054 | |
dc.language.iso | English | en_US |
dc.publisher | Taylor & Francis | en_US |
dc.relation.isversionof | http://dx.doi.org/10.1080/00207219308925844 | en_US |
dc.source.title | International Journal of Electronics | en_US |
dc.subject | Electric delay lines | en_US |
dc.subject | Electric wiring | en_US |
dc.subject | Electronics packaging | en_US |
dc.subject | Geometry | en_US |
dc.subject | Mathematical models | en_US |
dc.subject | Optimization | en_US |
dc.subject | Three dimensional | en_US |
dc.subject | Average signal delay | en_US |
dc.subject | Interconnect scaling rules | en_US |
dc.subject | Optimal linewidth distribution | en_US |
dc.subject | Resistor capacitor (RC) limited circuits | en_US |
dc.subject | Integrated circuit layout | en_US |
dc.title | Optimal linewidth distribution minimizing average signal delay for RC limited circuits | en_US |
dc.type | Article | en_US |
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