Register file reliability enhancement through adjacent narrow-width exploitation

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dc.citation.epage4en_US
dc.citation.spage1en_US
dc.contributor.authorAhangari, Hamzehen_US
dc.contributor.authorAlouani, I.en_US
dc.contributor.authorÖztürk, Özcanen_US
dc.contributor.authorNiar, S.en_US
dc.contributor.authorRivenq, A.en_US
dc.coverage.spatialIstanbul, Turkey
dc.date.accessioned2018-04-12T11:50:06Z
dc.date.available2018-04-12T11:50:06Z
dc.date.issued2016-04en_US
dc.departmentDepartment of Computer Engineeringen_US
dc.descriptionDate of Conference: 12-14 April 2016
dc.descriptionConference name: 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)
dc.description.abstractDue to the increasing vulnerability of CMOS circuits, new generations of microprocessors require an inevitable focus on reliability issues. As the Register File (RF) constitutes a critical element within the processor pipeline, it is mandatory to enhance the RF reliability to develop fault tolerant architectures. This paper proposes Adjacent Register Hardened RF (ARH), a new RF architecture that exploits the adjacent byte-level narrow-width values for hardening registers at runtime. Registers are paired together by some special switches referred to as joiners. Dummy sign bits of each register are used to keep redundant data of its counterpart register. We use 7T/14T SRAM cell [6] to combine redundant bits together to make a single bit cell which is, by far, more resilient against faults. Our simulations show that with 3% to 12% power overhead and 10% to 20% increase in area, in comparison to baseline RF, we can obtain up to 80% reduction in soft error rate (SER). © 2016 IEEE.en_US
dc.description.provenanceMade available in DSpace on 2018-04-12T11:50:06Z (GMT). No. of bitstreams: 1 bilkent-research-paper.pdf: 179475 bytes, checksum: ea0bedeb05ac9ccfb983c327e155f0c2 (MD5) Previous issue date: 2016en
dc.identifier.doi10.1109/DTIS.2016.7483882en_US
dc.identifier.urihttp://hdl.handle.net/11693/37751
dc.language.isoEnglishen_US
dc.publisherIEEEen_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/DTIS.2016.7483882en_US
dc.source.title2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)en_US
dc.subject7T/14T SRAMen_US
dc.subjectNarrow-widthen_US
dc.subjectRegister fileen_US
dc.subjectReliabilityen_US
dc.subjectSERen_US
dc.subjectSoft error rateen_US
dc.subjectHardeningen_US
dc.subjectIntegrated controlen_US
dc.subjectNanotechnologyen_US
dc.subjectRadiation hardeningen_US
dc.subjectCritical elementsen_US
dc.subjectFault-tolerant architecturesen_US
dc.subjectNarrow widthen_US
dc.subjectProcessor pipelinesen_US
dc.subjectRegister filesen_US
dc.subjectReliability enhancementen_US
dc.subjectRF reliabilityen_US
dc.subjectSoft error rateen_US
dc.titleRegister file reliability enhancement through adjacent narrow-width exploitationen_US
dc.typeConference Paperen_US

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