Energy efficient architecture for graph analytics accelerators

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dc.citation.epage177en_US
dc.citation.spage166en_US
dc.contributor.authorÖzdal, Muhammet Mustafaen_US
dc.contributor.authorYeşil, Şerifen_US
dc.contributor.authorKim, T.en_US
dc.contributor.authorAyupov, A.en_US
dc.contributor.authorGreth, J.en_US
dc.contributor.authorBurns, S.en_US
dc.contributor.authorÖztürk, Özcanen_US
dc.coverage.spatialSeoul, South Korea
dc.date.accessioned2018-04-12T11:49:10Z
dc.date.available2018-04-12T11:49:10Z
dc.date.issued2016-06en_US
dc.departmentDepartment of Computer Engineeringen_US
dc.descriptionDate of Conference: 18-22 June 2016
dc.descriptionConference name: ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA) 2016
dc.description.abstractSpecialized hardware accelerators can significantly improve the performance and power efficiency of compute systems. In this paper, we focus on hardware accelerators for graph analytics applications and propose a configurable architecture template that is specifically optimized for iterative vertex-centric graph applications with irregular access patterns and asymmetric convergence. The proposed architecture addresses the limitations of the existing multi-core CPU and GPU architectures for these types of applications. The SystemC-based template we provide can be customized easily for different vertex-centric applications by inserting application-level data structures and functions. After that, a cycle-accurate simulator and RTL can be generated to model the target hardware accelerators. In our experiments, we study several graph-parallel applications, and show that the hardware accelerators generated by our template can outperform a 24 core high end server CPU system by up to 3x in terms of performance. We also estimate the area requirement and power consumption of these hardware accelerators through physical-aware logic synthesis, and show up to 65x better power consumption with significantly smaller area. © 2016 IEEE.en_US
dc.identifier.doi10.1109/ISCA.2016.24en_US
dc.identifier.urihttp://hdl.handle.net/11693/37725
dc.language.isoEnglishen_US
dc.publisherIEEEen_US
dc.relation.isversionofhttps://doi.org/10.1109/ISCA.2016.24en_US
dc.source.titleProceedings - 43rd International Symposium on Computer Architecture, ISCA 2016en_US
dc.subjectHardware
dc.subjectInstruction sets
dc.subjectGraphics processing units
dc.subjectData structures
dc.subjectBandwidth
dc.subjectConvergence
dc.subjectC++ language
dc.subjectComputer architecture
dc.subjectData structures
dc.subjectGraph grammars
dc.subjectHigh level synthesis
dc.subjectMicroprocessor chips
dc.subjectMultiprocessing systems
dc.subjectOptimisation
dc.subjectPower aware computing
dc.titleEnergy efficient architecture for graph analytics acceleratorsen_US
dc.typeConference Paperen_US

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