Optimizing shared cache behavior of chip multiprocessors

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Optimizing shared cache behavior of chip multiprocessors.pdf (7.44 MB)

Date

2009-12

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Source Title

MICRO 42 Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, 2009

Publisher

ACM

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Keywords

Algorithm, Experimentation, Processors, Design styles, Memory structure, Performance, Programming language, Computer software, Design, Experiments, Linguistics, Microprocessor chips, Multiprocessing systems, Optimization, Program compilers, Cache memory, Compilers

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http://hdl.handle.net/11693/28639

Published Version (Please cite this version)

http://dx.doi.org/10.1145/1669112.1669176

Collections

Scholarly Publications - Computer Engineering

Language

English

Type

Conference Paper

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