Laser fabrication of in-chip multi-layer micro-channels

Abstract

For over half a century, the trend towards miniaturization resulted in great advances in electronic devices and computation. However, this is recently challenged by the emerging "heat-wall", a term indicating the limitation in heat extraction capability precludes further increasing the clock rates of electronics and thus delays faster computation. The challenge of heat extraction is a critical contributor to the recent stalling of Moore's Law. A potential solution for the heat-wall problem is to exploit microfluidic channels, in order to deliver controlled amounts of cooling fluid into relevant parts of the chip. Such an innovative approach is shown recently using integrated microfluidics. However, such approaches constitute surface microchannels fabricated with conventional lithography techniques, involving expensive and complicated fabrication steps. Further, these strategies may not treat all hot spots over a chip, where microfluidic channels are challenged to have access to desired locations. Here, we propose a laser-based micro-fabrication approach for creating multi-layered microchannels at any depth in the bulk of silicon. Further, the method ensures that the optical quality of top wafer surface remains preserved for potential integration of on-chip elements. Previously, proof-of-concept 3D laser-sculpting of silicon wafers have been demonstrated. Here, we leverage this approach, and exploit a two-step method which involves nonlinear laser-writing deep inside Si, followed by selective chemical etching of modified areas. We demonstrate the first fully buried multi-layered arrays, curved geometries and advanced architecture control. We create in-chip microchannels with a high aspect ratio of 25. We investigate the scaling and feature size of structures and the flexibility in laser-writing modality; characterize selective etching rates; and achieve wafer surface protection exploiting photo-resist coatings. We further present early results for low channel-wall roughness (0.23 μm) using modulated beams, and fabricate vertical micro-channels, i.e., "through silicon vias". The created multi-layer channel architectures with unscathed wafer surfaces have significant potential for use in heat-engineering of integrated systems.