Parallel maze routing algorithms on a hypercube multicomputer

Abstract

Global routing phase is a time consuming task in VLSI layout. In global routing phase of the layout problem, the overall objective is to realize all the net interconnections using shortest paths. Efficient heuristics are used for the global routing phase. However, clue to the assumptions and constraints they impose, heuristics may fail to find a path for a net even if one exists. Re-routing is required for such nets. This re-routing phase requires the exhaustive search of the wiring area. Lee’s maze routing algorithm and Lee type maze routing algorithms are exhaustive search algorithms used in re-routing phase. These algorithms are computationally expensive algorithms and consume large amounts of computer time for large grid sizes. Hence, these algorithms are good candidates for parallelization. Also, these algorithms require large memory space to hold the wiring grid. Therefore, the effective parallelization of these algorithms require the partitioning of the computations and the grid among the processors. Hence, these algorithms can be parallelized on distributed-memory message passing multiprocessors (multicomputers). In this work, efficient parallel Lee type maze routing algorithms are developed for hypercube-connected multi computers. These algorithms are implemented on an Intel’s iPSC/2 hypercube multicomputer.