Zinc-oxide charge trapping memory cell with ultra-thin chromium-oxide trapping layer

buir.contributor.authorOkyay, Ali Kemal
dc.citation.epage116en_US
dc.citation.issueNumber11en_US
dc.citation.spage112en_US
dc.citation.volumeNumber3en_US
dc.contributor.authorEl Atab, N.en_US
dc.contributor.authorRizk, A.en_US
dc.contributor.authorOkyay, Ali Kemalen_US
dc.contributor.authorNayfeh, A.en_US
dc.date.accessioned2015-07-28T12:03:46Z
dc.date.available2015-07-28T12:03:46Z
dc.date.issued2013-11-13en_US
dc.departmentDepartment of Electrical and Electronics Engineeringen_US
dc.description.abstractA functional zinc-oxide based SONOS memory cell with ultra-thin chromium oxide trapping layer was fabricated. A 5 nm CrO2 layer is deposited between Atomic Layer Deposition (ALD) steps. A threshold voltage (Vt) shift of 2.6V was achieved with a 10V programming voltage. Also for a 2V Vt shift, the memory with CrO2 layer has a low programming voltage of 7.2V. Moreover, the deep trapping levels in CrO2 layer allows for additional scaling of the tunnel oxide due to an increase in the retention time. In addition, the structure was simulated using Physics Based TCAD. The results of the simulation fit very well with the experimental results providing an understanding of the charge trapping and tunneling physics. © 2013 Author(s)en_US
dc.identifier.doi10.1063/1.4832237en_US
dc.identifier.issn2158-3226
dc.identifier.urihttp://hdl.handle.net/11693/12898
dc.language.isoEnglishen_US
dc.publisherAIP Publishingen_US
dc.relation.isversionofhttp://dx.doi.org/10.1063/1.4832237en_US
dc.source.titleAIP Advancesen_US
dc.subjectProgramming Voltageen_US
dc.subjectRetention Timeen_US
dc.subjectSonos Memory Cellen_US
dc.subjectTrapping Layersen_US
dc.subjectTrapping Levelsen_US
dc.subjectTunnel Oxidesen_US
dc.titleZinc-oxide charge trapping memory cell with ultra-thin chromium-oxide trapping layeren_US
dc.typeArticleen_US

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