Fabrication of ALN/GAN MIS-Hemt with SIN as gate dielectric and performance enhancement with ALD deposited alumina

Abstract

Silicon based transistors reached a limit, especially for high power and high frequency applications due to their relatively low bandgap and breakdown voltage. With its higher bandgap and breakdown voltage, GaN based transistors are promising devices for high power and high frequency applications. In particular with its high mobility due to the 2D Electron Gas at its interface, AlN/GaN heterostructure is a promisimg option to be used for such applications. High Electron Mobility Transistors(HEMT) fabricated on this heterostructure can work under higher voltages and higher frequencies when compared with standard silicon based transistors due to these superior properties. Also, as current electronics technology is mostly depend on Silicon based circuits, fabrication of these AlN/GaN HEMTs on Silicon substrates will provide easiness to integrate this technology to current systems. However, these transistors can suer from high leakage currents, which can cause a high power consumption problem. One solution to this problem is depositing a dielectric under gate area and such kind of transistors are called as MIS-HEMTs. In this thesis, MOCVD grown AlN/GaN on Silicon samples are used for fabrication of MIS-HEMTs. Before the fabrication of the transistors, a study on formation of ohmic contacts on these samples is performed. Then, two different AlN/GaN MIS-HEMTs with different gate dielectrics are fabricated and characterized. First type of samples have MOCVD grown SiN as gate dielectric and for second type of transistors, an alumina layer is deposited with ALD on top of SiN under gate area to decrease the gate leakage. Both of the transistors can remain gate control up to +2V gate bias. At least a three order of magnitude of decrease in gate leakage current is observed for high negative gate biases after deposition of alumina. Also, a gate leakage current in the order of 10¯¹º-10¯¹¹ A is observed for lower negative biases. A peak transconductance of 2:57mS is obtained for the transistors with gate length of 2µm, which is decreased to 1:71mS after alumina deposition.