Compiler-supported selective software fault tolerance

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buir.contributor.authorTurhan, Tuncer
buir.contributor.authorÖztürk, Özcan
dc.citation.epage6en_US
dc.citation.spage1
dc.contributor.authorTurhan, Tuncer
dc.contributor.authorTekgul, H.
dc.contributor.authorÖztürk, Özcan
dc.coverage.spatialTampa, FL, USA
dc.date.accessioned2024-03-07T09:57:01Z
dc.date.available2024-03-07T09:57:01Z
dc.date.issued2023-11-15
dc.departmentDepartment of Computer Engineering
dc.descriptionConference Name: 2023 IEEE Conference on Dependable and Secure Computing (DSC)
dc.descriptionDate of Conference: 07-09 November 2023
dc.description.abstractAs technology advances, the processors are shrunk in size and manufactured using higher-density transistors, making them cheaper, more power efficient, and more powerful. While this progress is most beneficial to end-users, these advances make processors more vulnerable to outside radiation, causing soft errors, mostly in single-bit flips on data. In applications where a certain margin of error is acceptable, and availability is important, the existing software fault tolerance techniques may not be applied directly because of the unacceptable performance overheads they introduce to the system. We propose a technique that ranks the instructions in terms of their criticality and generates a more reliable source code. This way, we improve reliability and minimize the performance overheads.
dc.identifier.doi10.1109/DSC61021.2023.10354221
dc.identifier.eisbn979-8-3503-8211-2
dc.identifier.isbn979-8-3503-8212-9
dc.identifier.urihttps://hdl.handle.net/11693/114382
dc.language.isoen_US
dc.publisherIEEE
dc.relation.isversionofhttps://dx.doi.org/10.1109/DSC61021.2023.10354221
dc.source.title2023 IEEE Conference on Dependable and Secure Computing (DSC)
dc.subjectFault Tolerance
dc.subjectReliability
dc.subjectInstruction criticality
dc.subjectCompiler
dc.titleCompiler-supported selective software fault tolerance
dc.typeConference Paper

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