Reconfigurable CNN accelerator design using dataflow analysis

Abstract

Dataflow reconfigurability plays a crucial role in Convolutional Neural Network (CNN) acceleration by determining the optimal dataflow pattern for convolution operations. Fully reconfigurable architectures provide versatility and high resource utilization by supporting multiple dataflow options, but this comes with increased design complexity and operational overhead. On the other hand, non-reconfigurable architectures, optimized for a single dataflow pattern, deliver high efficiency for specific tasks but lack adaptability. This thesis introduces a novel intermediate dataflow reconfigurable CNN accelerator that balances flexibility and efficiency by integrating key dataflow patterns, enhancing adaptability and performance across diverse CNN applications. Through a detailed analysis, key dataflows are identified, and a unique architectural unit is developed for dataflow selection, with an average of 0.15% excess latency compared to the optimal scenario. Our specialized systolic array architecture accommodates various kernel sizes, providing an additional layer of reconfigurability. Our architecture requires 39% less area and 35% less power than fully reconfigurable designs. Additionally, it delivers an average of 33% better performance compared to non-reconfigurable architectures. In terms of efficiency, it provides a 7% increase over fully reconfigurable designs and outperforms non-reconfigurable options by up to 3.57X.