Novel materials for thin-film memory cells

Abstract

The tremendous growth in consumer electronics market increased the need for low-cost, low-power and high quality memory chips. This challenge is further aggravated by the continuous increase in density and scaling of the gate length, since it creates a major challenge for current nonvolatile flash memory devices to maintain reliability and retention. Therefore, it is imperative to find new materials and novel fabrication processes to be incorporated in memory cells in order to keep up with the enormous rate of increase in consumer needs. In the first part of this thesis, we demonstrate a charge trapping memory with graphene nanoplatelets embedded in atomic layer deposited ZnO. We first introduce the fabrication process for the memory device and then investigate the memory characteristics. Our experimental analysis on the memory cell shows a large threshold voltage Vt shift (4V ) at low operating voltages (6/ − 6V ), good retention (> 10 years), and good endurance characteristics (> 104 cycles). The resulting memory behavior is also verified by theoretical computations. In the second part, we demonstrate the use of laser-synthesized indium-nitride nanoparticles (InN-NPs) as the charge trapping layer in the memory cell. We first introduce the indium-nitride nanoparticle synthesis and then detail the fabrication process of the memory device. The experimental analysis of the memory cell results in a noticeable threshold voltage Vt shift (2V ) at low operating voltages (4V ) in addition to the similar retention and endurance performance with the graphene-based memory cells. The memory behavior was also verified with theoretical computations for the InN-NPs based memory cells. In the last part of this thesis, we demonstrate a memory device with a gate stack fabricated in a single ALD step. Single-step all-ALD approach avoids the risk of contamination and incorporation of impurities in the gate stack. It also allows low-cost production by eliminating multiple equipment utilization. Motivated by these, we first present the fabrication process of the memory device and then explain the experimental and theoretical characterization and analysis. The memory effect of the thin-film ZnO charge-trapping memory cell is verified by a 2.35V hysteresis in drain current vs. gate voltage curve. The resulting memory behavior is also verified by physics-based TCAD simulations.