Browsing by Subject "Wafer-scale batch-compatible microfabrication"

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    Batch-compatible microfabrication of CMUT array chips for photoacoustic imaging of tissue-like phantoms (Part-II)
    (2024-01) Mahmood, Muhammad Rashid
    In this thesis study, Capacitive Micromachined Ultrasound Transducer (CMUT) array chips are microfabricated with wafer-scale batch-compatible approaches as sensors for photoacoustic imaging (PAI) applications. Photoacoustic imaging (PAI) is a non-invasive medical imaging technology, free from X-ray radiation, that utilizes contrast data resulting from acoustic detection of optical stimulation to construct images. CMUT array devices are microelectromechanical systems (MEMS) devices that generate or detect acoustic or pressure waves within the ultrasonic frequency range. The CMUT devices function on the principle of vibrating parallel plate variable capacitors. Capacitance variations due to vibrating plate electrode create electrical current signals in CMUT cells, which are further processed to obtain meaningful results. In PAI, pulsed laser light is transmit-ted and absorbed by naturally occurring photo-absorber compounds or contrast agents in selective body-tissue or tissue-like materials. The laser pulses are con-verted into heat, resulting in thermoelastic expansion vibrations of the tissue or tissue-like materials (i.e., phantom material). These vibrations travel as pressure or acoustic waves through the tissue or tissue-like materials that may be detected by CMUT sensors. For the production of the CMUT array devices, borosilicate glass (Pyrex-7740) wafers were selected as transparent substrates. The bottom electrode and electrical insulation layer above the bottom electrode of the CMUT sensors are processed on the Pyrex substrates. Anodic wafer bonding is selected as one of the suitable CMUT gap formation and top electrode integration technologies. Clean and unprocessed SOI (silicon-on-insulator) wafers are used for the formation of the top electrode of the CMUT sensors. The silicon handle layer and buried oxide (SiO2) layer of the SOI wafer are removed in order to reveal the silicon device layer that is used as the vibrating top electrode for the CMUT sensors. Metallization stacks on the Silicon device layer have been deposited for electrical conductivity enhancement and wire bonding connections between CMUT top electrodes and printed circuit boards (PCBs). After the patterning of the vibrating top electrode layer, dicing saw processing is done to singulate the CMUT chips from 4-inch diameter wafers. Chip-scale sealing of the CMUT chips is done by conformal Parylene C deposition using UV-sensitive dicing tape as a manual mask to prevent the deposition of Paylene C on the electrical pad regions of the CMUT chips. After Parylene C deposition, UV-sensitive dicing tape is re-moved from chips to reveal the electrical connection pads. CMUT array devices are characterized by inspecting their capacitive gap height, measuring their resonance frequencies, and determining the integration process yield. The resonance frequency results obtained from impedance analyzer measurements of individual CMUT cells are around 5.7 MHz. Furthermore, change in the resonance frequency is clearly detectable when the applied DC bias voltage is increased during the small AC plus incremental DC excitation of CMUT cell membranes.