Browsing by Subject "Viterbi Decoder"

Now showing 1 - 3 of 3

Open Access
BilRC: an execution triggered coarse grained reconfigurable architecture
(IEEE, 2013-07) Atak, O.; Atalar, Abdullah
We present Bilkent reconfigurable computer (BilRC), a new coarse-grained reconfigurable architecture (CGRA) employing an execution-triggering mechanism. A control data flow graph language is presented for mapping the applications to BilRC. The flexibility of the architecture and the computation model are validated by mapping several real-world applications. The same language is also used to map applications to a 90-nm field-programmable gate array (FPGA), giving exactly the same cycle count performance. It is found that BilRC reduces the configuration size about 33 times. It is synthesized with 90-nm technology, and typical applications mapped on BilRC run about 2.5 times faster than those on FPGA. It is found that the cycle counts of the applications for a commercial very long instruction word digital signal processor processor are 1.9 to 15 times higher than that of BilRC. It is also found that BilRC can run the inverse discrete cosine transform algorithm almost 3 times faster than the closest CGRA in terms of cycle count. Although the area required for BilRC processing elements is larger than that of existing CGRAs, this is mainly due to the segmented interconnect architecture of BilRC, which is crucial for supporting a broad range of applications.
Open Access
An execution triggered coarse grained recongigurable architecture
(2012) Atak, Oğuzhan
In this thesis, we present BilRC (Bilkent Reconfigurable Computer), a new coarse-grained reconfigurable architecture. The distinguishing feature of BilRC is its novel execution-triggering computation model which allows a broad range of applications to be efficiently implemented. In order to map applications onto BilRC, we developed a control data flow graph language, named LRC (a Language for Reconfigurable Computing). The flexibility of the architecture and the computation model are validated by mapping several real world applications. LRC is also used to map applications to a 90nm FPGA, giving exactly the same cycle count performance. It is found that BilRC reduces the configuration size about 33 times. It is synthesized with 90nm technology and typical applications mapped on BilRC run about 2.5 times faster than those on FPGA. It is found that the cycle counts of the applications for a commercial VLIW DSP processor are 1.9 to 15 times higher than that of BilRC. It is also found that BilRC can run the inverse discrete cosine transform algorithm almost 3 times faster than the closest CGRA in terms of cycle count. Although the area required for BilRC processing elements is larger than that of existing CGRAs, this is mainly due to the segmented interconnect architecture of BilRC, which is crucial for supporting a broad range of applications.
Open Access
FPGA based implementation of IEEE 80211a physical layer
(2010) İnce, Mustafa
Orthogonal Frequency Division Multiplexing (OFDM) is a multicarrier transmission technique, in which a single bitstream is transmitted over a large number of closely-spaced orthogonal subcarriers. It has been adopted for several technologies, such as Wireless Local Area Networks (WLAN), Digital Audio and Terrestrial Television Broadcasting and Worldwide Interoperability for Microwave Access (WiMAX) systems. In this work, IEEE802.11a WLAN standard was implemented on Field Programmable Gate Array (FPGA) for being familiar with the implementation problems of OFDM systems. The algorithms that are used in the implementation were firstly built up in MATLAB environment and the performance of system was observed with a simulator developed for this purpose. The transmitter and receiver FPGA implementations, which support the transmission rates from 6 to 54 Mbps, were designed in Xilinx System Generator Toolbox for MATLAB Simulink environment. The modulation technique and the Forward Error Coding (FEC) rate used at the transmitter are automatically adjusted by the desired bitrate as BPSK, QPSK, 16QAM or 64QAM and 1/2, 2/3 or 3/4, respectively.The transceiver utilizes 5986 slices, 45 block RAMs and 73 multipliers of a Xilinx Virtex-4 sx35 chip corresponding to % 39 of the resources. In addition, the FPGA implementation of the transceiver was also tested by constructing a wireless link between two Lyrtech Software Defined Radio Development Kits and the bit error rate of the designed system was measured by performing a digital loop-back test under an Additive White Gaussian Noise (AWGN) channel.