Browsing by Subject "Simulated Annealing"

Now showing 1 - 6 of 6

Open Access
Assembly line balancing using genetic algorithms
(1997) Tanyer, Muzaffer
For the last few decades, the genetic algorithms (GAs) have been used as a kind of heuristic in many areas of manufacturing. Facility layout, scheduling, process planning, and assembly line balancing are some of the areas where GAs are already popular. GAs are more efficient than traditional heuristics and also more flexible as they allow substantial changes in the problem’s constraints and in the solution approach with small changes in the program. For this reason, GAs attract the attention of both the researchers and practitioners. Chromosome structure is one of the key components of a GA. Therefore, in this thesis, we focus on the special structure of the assembly line balancing px'oblem and design a chromosome structure that operates dynamically. We propose a new mechanism to work in parallel with GAs, namely dynamic partitioning. Different from many other GA researchers, we particularly compare different population re\asion mechanisms and the effect of elitism on these mechanisms. Elitism is revised by the simulated annealing idea and various levels of elitism are created and their effects are observed. The proposed GA is £ilso compared with the traditional heuristics.
Open Access
Circuit partitioning using mean field annealing
(Elsevier, 1995) Bultan, T.; Aykanat, Cevdet
Mean field annealing (MFA) algorithm, proposed for solving combinatorial optimization problems, combines the characteristics of neural networks and simulated annealing. Previous works on MFA resulted with successful mapping of the algorithm to some classic optimization problems such as traveling salesperson problem, scheduling problem, knapsack problem and graph partitioning problem. In this paper, MFA is formulated for the circuit partitioning problem using the so called net-cut model. Hence, the deficiencies of using the graph representation for electrical circuits are avoided. An efficient implementation scheme, which decreases the complexity of the proposed algorithm by asymptotical factors is also developed. Comparative performance analysis of the proposed algorithm with two wellknown heuristics, simulated annealing and Kernighan-Lin, indicates that MFA is a successful alternative heuristic for the circuit partitioning problem. © 1995.
Open Access
A fast neural-network algorithm for VLSI cell placement
(Pergamon Press, 1998) Aykanat, Cevdet; Bultan, T.; Haritaoğlu, İ.
Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average.Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average.
Open Access
Parallel mapping and circuit partitioning heuristics based on mean field annealing
(1992) Bultan, Tevfik
Moan Field Annealinp; (MFA) aJgoritlim, receñí,ly proposc'd for solving com binatorial optimization problems, combines the characteristics of nenral networks and simulated annealing. In this thesis, MFA is formulated for tlie mapping i)roblcm and the circuit partitioning problem. EHicient implementation schemes, which decrease the complexity of the proposed algorithms by asymptotical factors, are also given. Perlormances of the proposed MFA algorithms are evaluated in comparison with two well-known heuristics: simulated annealing and Kernighan-Lin. Results of the experiments indicate that MFA can be used as an alternative heuristic for the mapping problem and the circuit partitioning problem. Inherent parallelism of the MFA is exploited by designing efficient parallel algorithms for the proposed MFA heuristics. Parallel MFA algorithms proposed for solving the circuit partitioning problem are implemented on an iPS(J/2’ hypercube multicompute.r. Experimental results show that the proposed heuristics can be efficiently parallelized, which is crucial for algorithms that solve such computationally hard problems.
Open Access
A simulation optimization for breast cancer screening in Turkey
(2014) Keyf, Dilek
Breast cancer is the most common cancer type among women in the world. 6.3 million women were diagnosed with breast cancer between 2007 - 2012 and 25% of cancers in women are breast cancer. Early diagnosis and early detection has an important role in survival from breast cancer. Mammographic screening is proved to be the only screening method that can reduce breast cancer mortality. Even though mammographic screening has this significant benefit, it is expensive and it can decrease life quality and it can generate false positive results. As a consequence, recommending an effective and costefficient mammographic screening policy in terms of starting and ending ages and screening frequencies has high importance. This study aims to optimize Ada’s Breast Cancer Simulation Model using Simulated Annealing. This model was run for Turkish women born in 1980 during their lifetime. The purpose of this study is to obtain an optimal or near optimal policy in terms of life years gained and cost for Turkish women. This study also aims to demonstrate the outcomes in terms of effectiveness and cost when different combinations of policy variables are used.
Open Access
Two novel multiway circuit partitioning algorithms using relaxed locking
(IEEE, 1997) Dasdan, A.; Aykanat, Cevdet
All the previous Kernighan-Lin-based (KL-based) circuit partitioning algorithms employ the locking mechanism, which enforces each cell to move exactly once per pass. In this paper, we propose two novel approaches for multiway circuit partitioning to overcome this limitation. Our approaches allow each cell to move more than once. Our first approach still uses the locking mechanism but in a relaxed way. It introduces the phase concept such that each pass can include more than one phase, and a phase can include at most one move of each cell. Our second approach does not use the locking mechanism at all. It introduces the mobility concept such that each cell can move as freely as allowed by its mobility. Each approach leads to KL-based generic algorithms whose parameters can be set to obtain algorithms with different performance characteristics. We generated three versions of each generic algorithm and evaluated them on a subset of common benchmark circuits in comparison with Sanchis' algorithm (FMS) and the simulated annealing algorithm (SA). Experimental results show that our algorithms are efficient, they outperform FMS significantly, and they perform comparably to SA. Our algorithms perform relatively better as the number of parts in the partition increases as well as the density of the circuit decreases. This paper also provides guidelines for good parameter settings for the generic algorithms. © 1997 IEEE.