Browsing by Subject "Off-chip"

Now showing 1 - 3 of 3

Open Access
Adaptive compute-phase prediction and thread prioritization to mitigate memory access latency
(ACM, 2014-06) Aktürk, İsmail; Öztürk, Özcan
The full potential of chip multiprocessors remains unex- ploited due to the thread oblivious memory access sched- ulers used in off-chip main memory controllers. This is especially pronounced in embedded systems due to limita- Tions in memory. We propose an adaptive compute-phase prediction and thread prioritization algorithm for memory access scheduling for embedded chip multiprocessors. The proposed algorithm eficiently categorize threads based on execution characteristics and provides fine-grained priori- Tization that allows to differentiate threads and prioritize their memory access requests accordingly. The threads in compute phase are prioritized among the threads in mem- ory phase. Furthermore, the threads in compute phase are prioritized among themselves based on the potential of mak- ing more progress in their execution. Compared to the prior works First-Ready First-Come First-Serve (FR-FCFS) and Compute-phase Prediction with Writeback-Refresh Overlap (CP-WO), the proposed algorithm reduces the execution time of the generated workloads up to 23.6% and 12.9%, respectively. Copyright 2014 ACM.
Open Access
Adaptive prefetching for shared cache based chip multiprocessors
(IEEE, 2009-04) Kandemir, M.; Zhang, Y.; Öztürk, Özcan
Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based CMP, multiple cores compete for the shared on-chip cache space and limited off-chip pin bandwidth. Purely software based prefetching techniques tend to increase this contention, leading to degradation in performance. In some cases, prefetches can become harmful by kicking out useful data from the shared cache whose next usage is earlier than the prefetched data, and the fraction of such harmful prefetches usually increases when we increase the number of cores used for executing a multi-threaded application code. In this paper, we propose two complementary techniques to address the problem of harmful prefetches in the context of shared L2 based CMPs. These techniques, namely, suppressing select data prefetches (if they are found to be harmful) and pinning select data in the L2 cache (if they are found to be frequent victim of harmful prefetches), are evaluated in this paper using two embedded application codes. Our experiments demonstrate that these two techniques are very effective in mitigating the impact of harmful prefetches, and as a result, we extract significant benefits from software prefetching even with large core counts. © 2009 EDAA.
Open Access
Design of high power S-band GaN MMIC power amplifiers for WiMAX applications
(IEEE, 2011) Cengiz, Ömer; Kelekçi, Özgür; Arıkan, Galip Orkun; Özbay, Ekmel; Palamutçuoǧullari O.
This paper reports two different S band GaN MMIC PA designs for WiMAX applications. First PA has a 42.6 dBm output power with a 55%PAE @ 3.5 GHz and 16 dB small signal gain in the 3.2-3.8 GHz frequency range. When two of these MMICs were combined by using off-chip Lange Couplers, 45.3 dBm output power with a 45%PAE @3.5Ghz and 16 dB small signal gain were obtained with less than 0.2 dB gain ripple in the 3.3-3.8 GHz frequency range. © 2011 IEEE.