Browsing by Subject "Nonvolatile storage"
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Item Open Access Cubic-phase zirconia nano-island growth using atomic layer deposition and application in low-power charge-trapping nonvolatile-memory devices(Institute of Physics Publishing Ltd., 2017) El-Atab, N.; Ulusoy, T. G.; Ghobadi, A.; Suh, J.; Islam, R.; Okyay, Ali Kemal; Saraswat, K.; Nayfeh, A.The manipulation of matter at the nanoscale enables the generation of properties in a material that would otherwise be challenging or impossible to realize in the bulk state. Here, we demonstrate growth of zirconia nano-islands using atomic layer deposition on different substrate terminations. Transmission electron microscopy and Raman measurements indicate that the nano-islands consist of nano-crystallites of the cubic-crystalline phase, which results in a higher dielectric constant (κ ∼ 35) than the amorphous phase case (κ ∼ 20). X-ray photoelectron spectroscopy measurements show that a deep quantum well is formed in the Al2O3/ZrO2/Al2O3 system, which is substantially different to that in the bulk state of zirconia and is more favorable for memory application. Finally, a memory device with a ZrO2 nano-island charge-trapping layer is fabricated, and a wide memory window of 4.5 V is obtained at a low programming voltage of 5 V due to the large dielectric constant of the islands in addition to excellent endurance and retention characteristics.Item Open Access Enhanced non-volatile memory characteristics with quattro-layer graphene nanoplatelets vs. 2.85-nm Si nanoparticles with asymmetric Al2O3/HfO2 tunnel oxide(Springer New York LLC, 2015) El-Atab, N.; Turgut, B. B.; Okyay, Ali Kemal; Nayfeh, M.; Nayfeh, A.In this work, we demonstrate a non-volatile metal-oxide semiconductor (MOS) memory with Quattro-layer graphene nanoplatelets as charge storage layer with asymmetric Al2O3/HfO2 tunnel oxide and we compare it to the same memory structure with 2.85-nm Si nanoparticles charge trapping layer. The results show that graphene nanoplatelets with Al2O3/HfO2 tunnel oxide allow for larger memory windows at the same operating voltages, enhanced retention, and endurance characteristics. The measurements are further confirmed by plotting the energy band diagram of the structures, calculating the quantum tunneling probabilities, and analyzing the charge transport mechanism. Also, the required program time of the memory with ultra-thin asymmetric Al2O3/HfO2 tunnel oxide with graphene nanoplatelets storage layer is calculated under Fowler-Nordheim tunneling regime and found to be 4.1 ns making it the fastest fully programmed MOS memory due to the observed pure electrons storage in the graphene nanoplatelets. With Si nanoparticles, however, the program time is larger due to the mixed charge storage. The results confirm that band-engineering of both tunnel oxide and charge trapping layer is required to enhance the current non-volatile memory characteristics.Item Open Access A heterogeneous memory organization with minimum energy consumption in 3D chip-multiprocessors(IEEE, 2016-05) Asad, Arghavan; Onsori, Salman; Fathy, M.; Jahed-Motlagh, M. R.; Raahemifar, K.Main memories play an important role in overall energy consumption of embedded systems. Using conventional memory technologies in future designs in nanoscale era cause a drastic increase in leakage power consumption and temperature-related problems. Emerging non-volatile memory (NVM) technologies offer many desirable characteristics such as near-zero leakage power, high density and non-volatility. They can significantly mitigate the issue of memory leakage power in future embedded chip-multiprocessor (eCMP) systems. However, they suffer from challenges such as limited write endurance and high write energy consumption which restrict them for adoption in modern memory systems. In this article, we propose a stacked hybrid memory system for 3D chip-multiprocessors to take advantages of both traditional and non-volatile memory technologies. For reaching this target, we present a convex optimization-based model that minimizes the system energy consumption while satisfy endurance constraint in order to design a reliable memory system. Experimental results show that the proposed method improves energy-delay product (EDP) and performance by about 44.8% and 13.8% on average respectively compared with the traditional memory design where single technology is used. © 2016 IEEE.Item Open Access Hybrid stacked memory architecture for energy efficient embedded chip-multiprocessors based on compiler directed approach(IEEE, 2015-12) Onsori, Salman; Asad, A.; Öztürk, Özcan; Fathy, M.Energy consumption becomes the most critical limitation on the performance of nowadays embedded system designs. On-chip memories due to major contribution in overall system energy consumption are always significant issue for embedded systems. Using conventional memory technologies in future designs in nano-scale era causes a drastic increase in leakage power consumption and temperature-related problems. Emerging non-volatile memory (NVM) technologies are promising replacement for conventional memory structure in embedded systems due to its attractive characteristics such as near-zero leakage power, high density and non-volatility. Recent advantages of NVM technologies can significantly mitigate the issue of memory leakage power. However, they introduce new challenges such as limited write endurance and high write energy consumption which restrict them for adoption in modern memory systems. In this article, we propose a stacked hybrid memory system to minimize energy consumption for 3D embedded chip-multiprocessors (eCMP). For reaching this target, we present a convex optimization-based model to distribute data blocks between SRAM and NVM banks based on data access pattern derived by compiler. Our compiler-assisted hybrid memory architecture can achieve up to 51.28 times improvement in lifetime. In addition, experimental results show that our proposed method reduce energy consumption by 56% on average compared to the traditional memory design where single technology is used. © 2015 IEEE.Item Open Access Implications of non-volatile memory as primary storage for database management systems(IEEE, 2017) Mustafa, Naveed Ul; Armejach, A.; Öztürk, Özcan; Cristal, A.; Unsal, O. S.Traditional Database Management System (DBMS) software relies on hard disks for storing relational data. Hard disks are cheap, persistent, and offer huge storage capacities. However, data retrieval latency for hard disks is extremely high. To hide this latency, DRAM is used as an intermediate storage. DRAM is significantly faster than disk, but deployed in smaller capacities due to cost and power constraints, and without the necessary persistency feature that disks have. Non-Volatile Memory (NVM) is an emerging storage class technology which promises the best of both worlds. It can offer large storage capacities, due to better scaling and cost metrics than DRAM, and is non-volatile (persistent) like hard disks. At the same time, its data retrieval time is much lower than that of hard disks and it is also byte-addressable like DRAM. In this paper, we explore the implications of employing NVM as primary storage for DBMS. In other words, we investigate the modifications necessary to be applied on a traditional relational DBMS to take advantage of NVM features. As a case study, we have modified the storage engine (SE) of PostgreSQL enabling efficient use of NVM hardware. We detail the necessary changes and challenges such modifications entail and evaluate them using a comprehensive emulation platform. Results indicate that our modified SE reduces query execution time by up to 40% and 14.4% when compared to disk and NVM storage, with average reductions of 20.5% and 4.5%, respectively. © 2016 IEEE.Item Open Access Matrix density effect on morphology of germanium nanocrystals embedded in silicon dioxide thin films(Materials Research Society, 2011) Alagoz, A. S.; Genisel, M. F.; Foss, Steinar; Finstad, T. G.; Turan, R.Flash type electronic memories are the preferred format in code storage at complex programs running on fast processors and larger media files in portable electronics due to fast write/read operations, long rewrite life, high density and low cost of fabrication. Scaling limitations of top-down fabrication approaches can be overcome in next generation flash memories by replacing continuous floating gate with array of nanocrystals. Germanium (Ge) is a good candidate for nanocrystal based flash memories due its small band gap. In this work, we present effect of silicon dioxide (SiO 2) host matrix density on Ge nanocrystals morphology. Low density Ge+SiO 2 layers are deposited between high density SiO 2 layers by using off-angle magnetron sputter deposition. After high temperature post-annealing, faceted and elongated Ge nanocrystals formation is observed in low density layers. Effects of Ge concentration and annealing temperature on nanocrystal morphology and mean size were investigated by using transmission electron microscopy. Positive correlation between stress development and nanocrystal size is observed at Raman spectroscopy measurements. We concluded that non-uniform stress distribution on nanocrystals during growth is responsible from faceted and elongated nanocrystal morphology.