Browsing by Subject "Gate length scaling"

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Open Access
Two-nanometer laser synthesized Si-nanoparticles for low power memory applications
(Springer International Publishing, 2016) El-Atab, N.; Okyay, Ali Kemal; Nayfeh, A.
Current flash memory devices are expected to face two major challenges in the near future: density and voltage scaling. The density of the memory is related to the gate length scaling which is constrained by the gate stack, namely, the tunnel oxide thickness. In fact, the gate length is required to be commensurate with the gate stack in order to maintain a good gate control and to avoid short channel effects. However, in conventional flash memories, the tunnel oxide thickness has a lower limit of 6-7 nm (depending on NOR or NAND structure) in order to avoid back-tunneling and thus leakage of charges which destroys the necessary retention characteristic of the memory (>10 years). The second problem which needs to be solved is the high program and erase operating voltages. Once again, the limitation to operating voltage scaling is the inability to reduce gate stack thickness. Therefore, it is imperative to find novel structures and materials to be incorporated in the memory cells which would allow tunnel oxide and voltage scaling. In this study, MOSFET- and MOSCAP-based memory devices are investigated along with the use of 2-nm silicon nanoparticles (Si-NPs) for charge storage. Atomic layer deposition is used to deposit the active layer of the memory and the spin coating is performed to deliver the Si-nanoparticles across the sample.