Browsing by Subject "Block lengths"

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    An FPGA implementation architecture for decoding of polar codes
    (IEEE, 2011) Pamuk, Alptekin
    Polar codes are a class of codes versatile enough to achieve the Shannon bound in a large array of source and channel coding problems. For that reason it is important to have efficient implementation architectures for polar codes in hardware. Motivated by this fact we propose a belief propagation (BP) decoder architecture for an increasingly popular hardware platform; Field Programmable Gate Array (FPGA). The proposed architecture supports any code rate and is quite flexible in terms of hardware complexity and throughput. The architecture can also be extended to support multiple block lengths without increasing the hardware complexity a lot. Moreover various schedulers can be adapted into the proposed architecture so that list decoding techniques can be used with a single block. Finally the proposed architecture is compared with a convolutional turbo code (CTC) decoder for WiMAX taken from a Xilinx Product Specification and seen that polar codes are superior to CTC codes both in hardware complexity and throughput. © 2011 IEEE.
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    Short length trellis-based codes for gaussian multiple-access channels
    (Institute of Electrical and Electronics Engineers Inc., 2014) Ozcelikkale, A.; Duman, T. M.
    We focus on trellis-based joint code design for two-user Gaussian multiple-access channel (MAC) in the short block length regime. We propose a design methodology, provide specific code designs and report numerical performance results. We compare the performance of the jointly designed codes with the performance of the codes designed for point-to-point (P2P) channels including optimum (in terms of minimum distance) convolutional codes. Our results show that the proposed codes achieve superior performance compared to these alternatives especially in the high signal-to-noise (SNR) regime in equal power scenarios.