Browsing by Author "Niar, S."

Now showing 1 - 6 of 6

Open Access
Adaptive routing framework for network on chip architectures
(ACM, 2016-01) Mustafa, Naveed Ul; Öztürk, Özcan; Niar, S.
In this paper we suggest and demonstrate the idea of applying multiple routing algorithms during the execution of a real application mapped on a Network-on-Chip (NoC). Traffic pattern of a real application may change during its execution. As performance of an algorithm depends on the traffic pattern, using the same routing algorithm for the entire span of execution may be inefficient. We study the feasibility of this idea for applications such as SPARSE and MPEG-4 decoder, by applying different routing algorithms. By applying more than one routing algorithms, throughput improves up to 17.37% and 6.74% in the case of SPARSE and MPEG-4 decoder applications, respectively, as compared to the application of single routing algorithm. © 2016 ACM.
Open Access
A novel heterogeneous approximate multiplier for low power and high performance
(Institute of Electrical and Electronics Engineers, 2018) Alouani, I.; Ahangari, Hamzeh; Öztürk, Özcan; Niar, S.
Approximate computing is a design paradigm considered for a range of applications that can tolerate some loss of accuracy. In fact, the bottleneck in conventional digital design techniques can be eliminated to achieve higher performance and energy efficiency by compromising accuracy. In this letter, a new architecture that engages accuracy as a design parameter is presented, where an approximate parallel multiplier using heterogeneous blocks is implemented. Based on design space exploration, we demonstrate that introducing diverse building blocks to implement the multiplier rather than cloning one building block achieves higher precision results. We show experimental results in terms of precision, delay, and power dissipation as metrics and compare with three previous approximate designs. Our results show that the proposed heterogeneous multiplier achieves more precise outputs than the tested circuits while improving performance and power tradeoffs.
Open Access
NS-SRAM: neighborhood solidarity SRAM for reliability enhancement of SRAM memories
(IEEE, 2016-08-09) Alouani, I.; Ahangari, Hamzeh; Öztürk, Özcan; Niar, S.
Technology shift and voltage scaling increased the susceptibility of Static Random Access Memories (SRAMs) to errors dramatically. In this paper, we present NS-SRAM, for Neighborhood Solidarity SRAM, a new technique to enhance error resilience of SRAMs by exploiting the adjacent memory bit data. Bit cells of a memory line are paired together in circuit level to mutually increase the static noise margin and critical charge of a cell. Unlike existing techniques, NS-SRAM aims to enhance both Bit Error Rate (BER) and Soft Error rate (SER) at the same time. Due to auto-adaptive joiners, each of the adjacent cells' nodes is connected to its counterpart in the neighbor bit. NS-SRAM enhances read-stability by increasing critical Read Static Noise Margin (RSNM), thereby decreasing faults when circuit operates under voltage scaling. It also increases hold-stability and critical charge to mitigate soft-errors. By the proposed technique, reliability of SRAM based structures such as cache memories and register files can drastically be improved with comparable area overhead to existing hardening techniques. Moreover it does not require any extra-memory, does not impact the memory effective size, and has no negative impact on performance. © 2016 IEEE.
Open Access
Power‐efficient reliable register file for aggressive‐environment applications
(Institution of Engineering and Technology, 2020) Alouani, I.; Ahangari, Hamzeh; Öztürk, Özcan; Niar, S.
In a context of increasing demands for on‐board data processing, insuring reliability under reduced power budget is a serious design challenge for embedded system manufacturers. Particularly, embedded processors in aggressive environments need to be designed with error hardening as a primary goal, not an afterthought. As Register File (RF) is a critical element within the processor pipeline, enhancing RF reliability is mandatory to design fault immune computing systems. This study proposes integer and floating point RF reliability enhancement techniques. Specifically, the authors propose Adjacent Register Hardened RF, a new RF architecture that exploits the adjacent byte‐level narrow‐width values for hardening integer registers at runtime. Registers are paired together by special switches referred to as joiners and non‐utilised bits of each register are exploited to enhance the reliability of its counterpart register. Moreover, they suggest sacrificing the least significant bits of the Mantissa to enhance the reliability of the floating point critical bits, namely, Exponent and Sign bits. The authors’ results show that with a low power budget compared to state of the art techniques, they achieve better results under both normal and highly aggressive operating conditions.
Open Access
Reconfigurable hardened latch and flip-flop for FPGAs
(IEEE, 2017-07) Ahangari, Hamzeh; Alouani, I.; Öztürk, Özcan; Niar, S.
In this paper, we propose Joint Latch (JLatch) and Joint Flip-Flop (JFF), two novel reconfigurable structures which bring the reconfigurability of reliability to user latches and flip-flops (FFs) in reconfigurable devices such as FPGAs. Specifically, we implement two reconfigurable storage elements that exploit a trade-off between reliability and amount of available resources. In fault prone conditions, JLatch (or JFF) is configured in such a way that four pre-selected normal static latches (or FFs) are combined together at circuit level to form one hardened storage cell. Solution focuses on transient faults such as soft errors, where we show that critical charge is increased by at least three orders of magnitude (1000X) to practically bring immunity against any Single Event Upset (SEU). If four latches inside an FPGA logic block are far enough, it can effectively cope with Multiple Bit Upsets (MBUs) as well. Additionally, provided that special transistor sizing is applied (only necessary for some latch structures), JLatch and JFF take advantage of a novel self-correcting technique to correct any single fault immediately. Our solution provides reconfigurability of reliability with negligible performance and area overhead with only one (two) extra transistor(s) per latch (FF). The delay of this technique is less than the delay of conventional TMR (Triple Modular Redundancy) technique with a majority voter at output. © 2017 IEEE.
Open Access
Register file reliability enhancement through adjacent narrow-width exploitation
(IEEE, 2016-04) Ahangari, Hamzeh; Alouani, I.; Öztürk, Özcan; Niar, S.; Rivenq, A.
Due to the increasing vulnerability of CMOS circuits, new generations of microprocessors require an inevitable focus on reliability issues. As the Register File (RF) constitutes a critical element within the processor pipeline, it is mandatory to enhance the RF reliability to develop fault tolerant architectures. This paper proposes Adjacent Register Hardened RF (ARH), a new RF architecture that exploits the adjacent byte-level narrow-width values for hardening registers at runtime. Registers are paired together by some special switches referred to as joiners. Dummy sign bits of each register are used to keep redundant data of its counterpart register. We use 7T/14T SRAM cell [6] to combine redundant bits together to make a single bit cell which is, by far, more resilient against faults. Our simulations show that with 3% to 12% power overhead and 10% to 20% increase in area, in comparison to baseline RF, we can obtain up to 80% reduction in soft error rate (SER). © 2016 IEEE.