Browsing by Author "Bultan, T."

Filter results by typing the first few letters
Now showing 1 - 3 of 3
  • Thumbnail Image
    ItemOpen Access
    Circuit partitioning using mean field annealing
    (Elsevier, 1995) Bultan, T.; Aykanat, Cevdet
    Mean field annealing (MFA) algorithm, proposed for solving combinatorial optimization problems, combines the characteristics of neural networks and simulated annealing. Previous works on MFA resulted with successful mapping of the algorithm to some classic optimization problems such as traveling salesperson problem, scheduling problem, knapsack problem and graph partitioning problem. In this paper, MFA is formulated for the circuit partitioning problem using the so called net-cut model. Hence, the deficiencies of using the graph representation for electrical circuits are avoided. An efficient implementation scheme, which decreases the complexity of the proposed algorithm by asymptotical factors is also developed. Comparative performance analysis of the proposed algorithm with two wellknown heuristics, simulated annealing and Kernighan-Lin, indicates that MFA is a successful alternative heuristic for the circuit partitioning problem. © 1995.
  • Thumbnail Image
    ItemOpen Access
    A fast neural-network algorithm for VLSI cell placement
    (Pergamon Press, 1998) Aykanat, Cevdet; Bultan, T.; Haritaoğlu, İ.
    Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average.Cell placement is an important phase of current VLSI circuit design styles such as standard cell, gate array, and Field Programmable Gate Array (FPGA). Although nondeterministic algorithms such as Simulated Annealing (SA) were successful in solving this problem, they are known to be slow. In this paper, a neural network algorithm is proposed that produces solutions as good as SA in substantially less time. This algorithm is based on Mean Field Annealing (MFA) technique, which was successfully applied to various combinatorial optimization problems. A MFA formulation for the cell placement problem is derived which can easily be applied to all VLSI design styles. To demonstrate that the proposed algorithm is applicable in practice, a detailed formulation for the FPGA design style is derived, and the layouts of several benchmark circuits are generated. The performance of the proposed cell placement algorithm is evaluated in comparison with commercial automated circuit design software Xilinx Automatic Place and Route (APR) which uses SA technique. Performance evaluation is conducted using ACM/SIGDA Design Automation benchmark circuits. Experimental results indicate that the proposed MFA algorithm produces comparable results with APR. However, MFA is almost 20 times faster than APR on the average.
  • Thumbnail Image
    ItemOpen Access
    A new mapping heuristic based on mean field annealing
    (Academic Press, 1992) Bultan, T.; Aykanat, Cevdet
    A new mapping heuristic is developed, based on the recently proposed Mean Field Annealing (MFA) algorithm. An e cient implementation scheme, which decreases the complexity of the proposed algorithm by asymptotical factors, is also given. Performance of the proposed MFA algorithm is evaluated in comparison with two wellknown heuristics; Simulated Annealing and Kernighan-Lin. Results of the experiments indicate that MFA can be used as an alternative heuristic for solving the mapping problem. Inherent parallelism of MFA is exploited by designing an e cient parallel algorithm for the proposed MFA heuristic.